International Business Machines Corporation

Globalfoundries Inc.

Macom Technology Solutions Holdings, Inc.

Yan Zhang

Jeffrey P Gambino

Qizhi Liu

Zhenzhen Ye

Edward J Nowak

Brent A Anderson

Wayne Mack Struble

Shimin Cui

Allen W Hanson

Gabriel R Cueva

An apparatus includes a channel layer, a first layer, a hole barrier layer and a second layer. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valence band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally forms a field effect transistor.

Transistor with hole barrier layer

The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material.

Inductor heat dissipation in an integrated circuit

According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide.

Heat dissipation through device isolation

Embodiments relate to data splitting for multi-instantiated objects. An aspect includes receiving a portion of source code for compilation having a dynamic object to split using object size array data splitting. Another aspect includes replacing all memory allocations for the dynamic object with a total size of an object size array and object field arrays including a predetermined padding. Another aspect includes inserting statements in the source code after the memory allocations to populate the object size array with a value of a number of elements of the object size array. Another aspect includes updating a stride for load and store operations using dynamic pointers. Yet another aspect includes modifying field references by adding a distance between the object size array and the object field array to respective address operations.

Data splitting for multi-instantiated objects

Disclosed are gate-all-around (GAA) field effect transistors (FETs) and methods of forming them. In one GAAFET, a semiconductor body is on an insulator layer. A gate wraps around the semiconductor body (i.e., is adjacent to the top, bottom and opposing sides of the semiconductor body) at a channel region with a lower portion of the gate being in a cavity in the insulator layer. In another GAAFET, multiple semiconductor bodies are on an insulator layer. A gate wraps around and extends between the semiconductor bodies at channel regions with a lower portion of the gate being contained in a cavity in the insulator layer. To reduce gate resistance and gate-to-source/drain contact capacitance, the lower portion extends a greater distance below the bottom(s) of the semiconductor body(ies) than the upper portion extends above the top(s). To further reduce gate resistance, the length and width of the lower portion increases from the top surface of the insulator layer downward.

Gate-all-around field effect transistor structures and methods

Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.

Semiconductor-on-insulator (SOI) structures with local heat dissipater(s) and methods

An isolation structure can include a structure material with thermal conductivity greater than silicon dioxide, yet electrical conductivity such that the structure material can replace silicon dioxide as an insulator. At least one column can extend to a target layer from a top surface of a semiconductor device near an active area of the device. At least one lateral portion can extend from the column(s) substantially parallel to the target layer and can extend between multiple columns in the target layer, such as in a cavity formed by lateral etching. The structure material can include, for example, aluminum nitride (AlN).

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South Burlington, VT, United States of America

Yan Zhang