Intel Corporation

Yan Xu

Joshua J Ratcliff

Maha El Choubassi

Kenneth P Griesser

James Earl White

Richard Brunner

Chandrashekhar S Patwardhan

Oscar Nestares

Steven J Tu

Alexey Supikov

Ronald T Azuma

Deif N Atallah

Gheric Speiginer

Murtuza Ali Lakhani

A plurality of frames of a video recorded by a video camera and depth maps of the plurality of frames are stored in a data storage. One or more target video camera positions are determined. Each frame of the plurality of frames is associated with one or more of the target video camera positions. For each frame, one or more synthesized frames from the viewpoint of the one or more target camera positions associated with that frame are generated by applying a view interpolation algorithm to that frame using the color pixels of that frame and the depth map of that frame. Users can provide their input about the new camera positions and other camera parameters through multiple input modalities. The synthesized frames are concatenated to create a modified video. Other embodiments are also described and claimed.

View interpolation for visual storytelling

This application is directed to dynamic control for data capture. A device may comprise a capture logic module to receive at least one of biometric data from a biometric sensing module, context data from a context sensing module or content data from a content sensing module. The capture logic module may determine if a capture scenario exists based on at least one of the biometric data and context data. The determination may be weighted based on an operational mode. If a capture scenario is determined to exist, the capture logic module may then determine whether to capture data based on at least the content data. Captured data may be stored in a capture database in the device (e.g., along with enhanced metadata based on at least one of the biometric data, the context data or the content data). The device may also comprise a feedback database including feedback data.

Dynamic control for data capture

Embodiments for image capture feedback are disclosed. In some embodiments, a computing system may receive a first image from an image capture device and generate a score for the first image. The computing system may generate a recommendation for an action, such that if the image capture device captures a second image after the action is performed, the score for the second image will be better than the score for the first image. The computing system may indicate the recommended action to the user on an output device. Other embodiments may be disclosed and/or claimed.

Image capture feedback

A method and apparatus for providing full accessibility to on-chip instruction cache and microcode ROM are described. A dummy tag and a dummy instruction are written into a cache tag array and an instruction array, respectively, during a test mode. The dummy tag is concatenated with a predetermined set number and a predetermined word address to form a dummy address having a dummy tag field, a set field and a word address field. An instruction fetch is invoked using the dummy address. The instruction cache is accessed with the dummy address, and a cache miss is forced to occur. The dummy tag field of the dummy address is written into the tag array at a row specified by the predetermined set number, and the dummy instruction is written into the instruction array at the same row. Execution of the dummy instruction is suppressed. A read operation is performed in a similar manner, except in that case an instruction cache hit is forced to occur to cause data to be read from the instruction cache. Execution of the data read from the cache is suppressed. Microcode ROM is also read by invoking a dummy instruction fetch. The dummy instruction fetch causes data to be retrieved from a predetermined address in the ROM. Execution of the retrieved data is suppressed.

Method and apparatus for providing full accessibility to instruction cache and microcode ROM

The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified. The external event is asserted when there is a match between the target instruction address and a pipeline instruction pointer corresponding to a second pipeline stage. The second pipeline stage is earlier than the first pipeline stage in the pipeline chain. The external event is unmasked via a delivery path between a signal representing the asserted external event and the first pipeline stage.

Injection control mechanism for external events

A method and apparatus for providing full accessibility to on-chip instruction cache and microcode ROM are described. A dummy tag and a dummy instruction are written into a cache tag array and an instruction array, respectively, during a test mode. The dummy tag is concatenated with a predetermined set number and a predetermined word address to form a dummy address having a dummy tag field, a set field and a word address field. An instruction fetch is invoked using the dummy address. The instruction cache is accessed with the dummy address, and a cache miss is forced to occur. The dummy tag field of the dummy address is written into the tag array at a row specified by the predetermined set number, and the dummy instruction is written into the instruction array at the same row. Execution of the dummy instruction is suppressed. A read operation is performed in a similar manner, except in that case an instruction cache hit is forced to occur to cause data to be read from the instruction cache. Execution of the data read from the cache is suppressed. Microcode ROM is also read by invoking a dummy instruction fetch The dummy instruction fetch causes data to be retrieved from a predetermined address in the ROM. Execution of the retrieved data is suppressed.

Method and apparatus for providing test mode access to an instruction

Methods and apparatus for interactive built-in self-testing with user-programmable test patterns are disclosed. The present invention operates in the context of an integrated circuit (IC) including built-in self-test (BIST) logic and a test interface circuit resident on the IC. The BIST logic executes a BIST routine for testing the IC, and the test interface achieves the inputting of an external test pattern into the BIST logic from an external logic circuit. The test interface includes a first flag storage element accessible to the BIST logic. The first flag storage element stores a first flag that indicates whether the test pattern will be provided to the IC from the external logic. A test data storage element in the test interface stores the external test pattern, and is also accessible to the BIST logic. A second flag storage element accessible to the BIST logic stores a second flag to indicate whether the test pattern is available in the test data storage element. Test control logic receives a first instruction from the external logic, and executes the first instruction to set the first flag. The test control logic reads the test pattern and sets the second flag after the test pattern is stored in the test data storage element. If the first flag is not set, the BIST logic executes the BIST routine using a test pattern internally generated on the IC. On the other hand, if the first flag is set, then the BIST logic executes the BIST routine using the test patterns stored in the test data storage element.

Method and apparatus for interactive built-in-self-testing with

A system which is able to perform unaligned big endian and little endian accesses to memory with little or no added overhead to the system. In the preferred embodiment, the processor operates in little endian data format. The memory, however, can store data in big endian and little endian format in different memory regions. If an unaligned access is to be performed, the access requires translation to corresponding aligned memory accesses. However, if the processor operates in little endian format and accesses are to memory which store according big endian format, special code is required to perform proper translation of accesses. When the address generation unit of the processor detects an unaligned memory access, an unaligned signal is set which causes a microassist to initiate a microflow to execute microcode which performs the necessary translations for unaligned accesses. The address generation unit also sends the address to be access to the memory region table which maintains information regarding each memory region, including whether the region is big endian or little endian. The state bit indicative of the data format is logically combined with the unaligned access signal to generate an output which sets the state of the flag. The flag is then accessed by the microcode to determine the translation routine to process the memory access.

Growing community of inventors

Santa Clara, CA, United States of America

Yan Xu