Freescale Semiconductor,inc.

Nxp Usa, Inc.

Yan Xiao

Wangsheng Mei

Joseph Charles Circello

Li Zhang

Liang Zhang

Jianzhou Wu

Martin Mienkina

Zhijun Chen

Zhiling Sui

Su-fen Wei

A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. The at least one operation decoder component is arranged to, upon receipt of a write access request via the interconnect component corresponding to a decorated memory-mapped address range for the hardware interface component, decode a register identifier component of a target address of the received write access request to identify at least one of the program-visible registers, decode a decoration component of the target address of the received write access request to identify an arithmetic operation to be performed, and configure the arithmetic unit to perform the identified arithmetic operation on at least one input operand within the identified at least one program-visible register.

Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address

A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states.

True random number generator with repeatedly activated oscillator

A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.

FSK demodulator

An application processor circuit has SD-compatible interface protocols and can perform both host and slave functions. The circuit includes SD bus interface logic for realizing SD interface signals defined in SD-compatible interface protocols; system bus interface logic for performing the interface function on the system bus side; a data buffer for adjusting the data transfer rate difference between the SD bus interface and the system bus interface; a data buffer controller for controlling access to the data buffer; and a configuration unit for configuring the circuit to work in the host mode or slave mode. The SD-compatible interface protocols include MMC/SD/SDIO protocol, high speed MMC/SD/SDIO protocol, and CE-ATA interface protocol. The SD host logic and slave logic are incorporated in a single module to support both the SD host and slave functions, so as to achieve more convenient data transfer between electronic devices.

Application processor circuit incorporating both SD host and slave functions and electronic device including same

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Suzhou, China

Yan Xiao