Qualcomm Incorporated

Cytovia, Inc.

Euro-celtique S.a.

Other

Purdue Neuroscience Company

Cocensys Inc.

Yan Wang

Sui Xiong Cai

Nancy C Lan

Dinesh Jagannath Alladi

Eckard Weber

Cory Lee McCluskey

John A Drewe

Elias Dagher

John F W Keana

Gordon B Mills

Douglas R Green

George Field

Seyed Arash Mirhaj

David B Fick

Ravi Upasani

Qubo Zhou

Chieh-Yu Hsieh

Mohammad Meysam Zargham

Victor I Ilyin

Huilin Xu

Tom Chin

Kuo-Chun Lee

Jun Ma

Liangping Ma

Qiang Wu

Weimin Duan

Mehmet Izzet Gurelli

Changhwan Park

Vijayakumar Dhanasekaran

Shailaja Kasibhatla

Alexander Dorosenco

Han-Zhong Zhang

Lianghai Ji

Karthik Anantha Swamy

Lei Sun

Shan Qing

Omid Rajaee

Mohamad Sayed Hassan

Kshitij Yadav

Yuhua Guo

Xiaoning Lu

Ben Y Tseng

Aram Akhavan

Haiji Xia

Li Lu

Venkatraman Rajagopalan

Huan Xu

Onur Senel

Ji Ma

Lufeng Guan

Nitzan OFer

Methods, systems, and devices for wireless communication are described. A user equipment (UE) may obtain updated location information, and determine a time difference between a previous communication with a network and a scheduled uplink transmission. Based on the determined time difference, the UE may determine a timing advance (TA) component of a TA value to apply for the uplink transmission, and transmit an uplink message in the uplink transmission according to the determined TA value and the location information. In some examples, the time difference may be based on a first duration between the uplink transmission and a previous uplink transmission, a second duration between the uplink transmission and a previous TA command received from the network, or both. In some examples, the determined TA value may be based on additional parameters, such as an autonomous adjustment step, an aggregate adjustment rate, a scaling factor, or any combination thereof.

Techniques for timing adjustment

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

Pipelined analog-to-digital conversion

Disclosed are devices that can perform multiple independent digital PCRs with real-time monitoring capability. The device comprises multiple PCR mini-reactors thermally coupled with its own temperature control element, a detection unit, and a motor for moving the PCR mini-reactors or the detection unit. The real-time digital PCR device can simultaneously perform multiple digital PCRs, generate amplification curves of thousands and millions of individual PCR processes, evaluate binary readouts based on the kinetic properties of individual amplification curves, and identify different target sequences based on the amplification curves. Methods of using the real-time digital PCR device to detect target nucleic acids and count circulating tumor cells are also disclosed.

Methods and devices for performing real time digital PCR

Provided is a fluorescence reader that uses two excitation channels and can read up to seven different fluorescent dyes in a single run. Each excitation channel has one light source and one single excitation filter and one dichroic mirror. One excitation channel is capable of exciting multiple fluorescent dyes and can be used to distinguish multiple dyes in combination with multiple emission filters. The excitation channels are driven by a motor that can automatically switch the two excitation channels for taking images of up to seven different fluorescent dyes. An algorithm to calibrate the crosstalk between different fluorescent dyes is also provided. Also provided is a method for analyzing digital PCR data using a ratio of two fluorescence emission readings.

Method for correcting interference of multicolor fluorescence channels

Method for analyzing digital PCR data using multicolor fluorescence reader

An apparatus for power supply mode switching includes a first voltage regulator to output a first voltage, a second voltage regulator to output a second voltage, a third voltage regulator to output a third voltage, an electronic load, a first switch between the first voltage regulator and the electronic load, a second switch between the second voltage regulator and the electronic load, and a third switch between the third voltage regulator and the electronic load. And, a method for power supply mode switching includes supplying power to an electronic load with a first voltage; switching to a second voltage; maintaining coupling of the electronic load with the second voltage while a voltage across the electronic load is less than a reference voltage; and switching to a third voltage when the voltage is greater than or equal to the reference voltage and the third voltage is less than the second voltage.

Low-glitch switch control for mode switching of memory cells

Multicolor fluorescence reader with dual excitation channels

Certain aspects of the present disclosure generally relate to a power stage. The power stage generally includes a first transistor, a second transistor having a drain coupled to a drain of the first transistor, a first gate drive circuit coupled between an input node of the power stage and a gate of the first transistor, and a second gate drive circuit having a first signal path coupled between the input node and a gate of the second transistor. In certain aspects, the second gate drive circuit comprises a plurality of buffers in the first signal path, and a plurality of electronic devices coupled to the plurality of buffers and configured to apply a delay associated with driving the gate of the second transistor to track a delay associated with driving the gate of the first transistor via the first gate drive circuit.

Area-efficient non-overlapping signal generator

Disclosed is a method for aligning images of high-density signals of a dPCR chip with high precision and accuracy, which assigns each signal spot on an dPCR image to a unified grid. More specifically, the invention provides methods for adjusting the coordinates of signal spots in an image, and aligning the adjusted image to the unified grid by aligning to features of a fiducial marker built in the chip.

Methods for aligning images of digital PCR chips

Methods and apparatus are provided for aggressive beam selection during a handover procedure. A User Equipment (UE) measures a plurality of candidate downlink beams of a target base station (BS), wherein measurement opportunities for each of the candidate downlink beams are scheduled periodically. The UE reports measurements relating to one or more of the measured candidate downlink beams to a source BS. The UE receives a command to handover to the target BS, and in response to receiving the command, attempts to find a new downlink beam of the target BS having a corresponding measurement opportunity that is earlier than a next measurement opportunity of one of the one or more candidate downlink beam.

Aggressive beam selection during handover procedure

Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.

Successive approximation register analog-to-digital converter chopping

A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

Continuous-time analog-to-digital converter

Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

Continuous-time delta-sigma ADC with scalable sampling rates and excess loop delay compensation

Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.

Time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits for multi-channel receivers

A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Multi-mode discrete-time delta-sigma modulator power optimization using split-integrator scheme

Growing community of inventors

San Diego, CA, United States of America

Yan Wang