Hrl Laboratories, LLC

The Boeing Company

Yan Tang

Dean C Regan

Miroslav Micovic

Keisuke Shinohara

David F Brown

Joel C Wong

John J Vajo

Jeong-sun Moon

Hasan Sharifi

Florian G Herrault

Chia-Ming Chang

Andrea Corrion

Sevag Terterian

Ivan Milosavljevic

Charbel Abijaoude

Helen Fung

Helen Hor Ka Fung

A reversable attachment system includes an adhesion layer, an inter-substrate bond structure, a mating layer and an extension actuator. The adhesion layer is configured to attach to a first substrate. The inter-substrate bond structure is coupled to the adhesion layer. The mating layer is configured to attach to a second substrate. The extension actuator is configured to attach to the second substrate and expand in response to an absorption of a gas. The inter-substrate bond structure is configured to form an initial thermocompression bond with the mating layer in response to an applied pressure and an applied heat. The expansion of the extension actuator in response to absorbing the gas detaches the inter-substrate bond structure from the mating layer.

Reversable attachment system

An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said first component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip top surface; a first conductor connecting said wafer contact pad and said component contact pad.

Hybrid integrated circuit architecture

A self-aligned GaN FinFET device and a method of fabricating the same are disclosed. This self-aligned process helps to fabricate GaN FinFET devices in a scalable manner. This work transforms the T-gate process to incorporate fins to further improve pinch-off and decrease leakage currents on highly scaled GaN HEMT structures. The GaN FinFET structure will also allow for integration of normally-off devices with normally-on devices by varying the fin width. The FinFET improvement combines the fin structure consisting of various fin pitches and widths, gate dielectric, self-aligned gate design, ultra-low ohmic contacts, and vertically scaled epitaxy into a single scalable process.

Self-aligned gallium nitride FinFET and method of fabricating the same

A four-terminal GaN transistor and methods of manufacture, the transistor having source and drain regions and preferably two T-shaped gate electrodes, wherein a stem of one of the two T-shaped gate electrodes is more closely located to the source region than it is to a stem of the other one of the two T-shaped gate electrodes and wherein the stem of the other one of the two T-shaped gate electrodes is more closely located to the drain region than it is to the stem of said one of the two T-shaped gate electrodes. The the gate closer to the source region is a T-gate, and the proximity of the two gates is less than 500 nm from each other. The spacing between the stem of the RF gate and source region and the stem of the DC gate and drain region are preferably defined by self-aligned fabrication techniques. The four-terminal GaN transistor is capable of operation in the W-band (75 to 100 GHz).

Method of making a dual-gate HEMT

Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of making and using such devices and the operational benefits of the devices.

T-gate field effect transistor with non-linear channel layer and/or gate foot face

A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in some embodiments and in such embodiments the stem of the T-shaped gate is located relative to drain and source contacts of the device by forming a plurality of sidewall spacers, with more sidewall spacers being formed on the drain side of the stem than are formed on the source side of the stem. Additionally the gate stem preferably has a high aspect ratio to improve the performance of the resulting FET or HEMT. Drain and source contacts are preferably formed of an n+ semiconductor material.

Methods of fabricating self-aligned FETS using multiple sidewall spacers

A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.

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Oak Park, CA, United States of America

Yan Tang