Fujitsu Semiconductor Limited

Lattice Semiconductor Corporation

Yan Rui

Yu Shen

Kexin Luo

Rui Yin

Shaoyong Lu

Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.

Phase locked loop with sub-harmonic locking prevention functionality

A method and a system for obtaining motion vectors and boundary strengths of an image are disclosed. The method comprises the steps of: S, determining motion vector prediction direction information and motion vector calculation method information of a block to be decoded currently according to a type of the block to be decoded currently and a type of a macroblock/sub-macroblock in which the block to be decoded currently is located; S, obtaining related information needed to calculate a motion vector of the block to be decoded currently using the motion vector prediction direction information according to the motion vector calculation method information; and S, calculating the motion vector of the block to be decoded currently using the related information obtained, and calculating a boundary strength of the block to be decoded currently using the motion vector of the block to be decoded currently.

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Shanghai, China

Yan Rui