Macronix International Co., Ltd.

Au Optronics Corporation

Hon Hai Precision Industry Co., Ltd.

Yan-Ru Chen

Peng-Bo Xi

Wei-Chih Chien

Shih-Hung Chen

Ming-Hsiu Lee

Yen-Hao Shih

Teng-Hao Yeh

Yi-Chou Chen

Che-Chia Chang

Chen-Chi Lin

Yu-Chieh Kuo

Shang-Jie Wu

Mei-Yi Li

Chia-Che Hung

Yu-Hsun Chiu

Ting-Wei Guo

Chia-Ting Hsieh

Sheng-Yu Hsu

Lo-Yueh Lin

Cheng-Nan Yeh

En-Chih Liu

Kai-Hsiang Liu

Chin I Chiang

A memory chip includes a memory cell circuit, a periphery circuit, an interconnect structure, and a control logic circuit. The periphery circuit is positioned under the memory cell circuit and electrically connected to the memory cell circuit. The interconnect structure is positioned on a side surface of the memory cell circuit. The control logic circuit is positioned under the interconnect structure. The control logic circuit is electrically connected to the interconnect structure and the periphery circuit and includes a dynamic random-access memory.

Memory chip including control logic circuit with dynamic random-access memory and memory device including memory chips

A light-emitting diode display device and a light-emission control method thereof are provided. The light-emitting diode display device includes a timing controller, multiple display pixels, and a scanning circuit. The display pixels form multiple display rows. The scanning circuit generates multiple scan signals and multiple light-emission signals that respectively drive the display rows. During a first data-writing time period of a first frame period, the timing controller provides multiple writing data to be respectively written into the display rows. During a light-emitting time period, the scanning circuit drives each of the light-emission signals to generate multiple pulses periodically according to a set period to drive the corresponding display rows. The light-emitting time period is after the first data-writing time period and before a second data-writing time period of a second frame period ends.

Light-emitting diode display device and light-emission control method thereof

A display apparatus and a pixel circuit thereof are provided. The pixel circuit is configured to drive a light-emitting diode (LED). The pixel circuit includes a driving transistor, a switch, a data writing circuit, and a voltage selector. The switch is turned on during a data-writing time period, and cut-off during a laser time period. The data writing circuit transports a data voltage to a control terminal of the driving transistor during the data-writing time period. During the data-writing time period, a second terminal of the LED receives a first reference voltage, and during the laser time period, the second terminal of the LED receives a second reference voltage. The first reference voltage and the second reference voltage are different.

Display apparatus and pixel circuit thereof

A display panel and a pixel circuit of the display panel are provided. The pixel circuit includes a driving transistor and a light-emitting time length modulator. The driving transistor has a control terminal receiving a pulse width control signal and an amplitude control signal, and the driving transistor generates a driving signal. In a first time period, the light-emitting time length modulator modulates a time length of a plurality of second time periods for providing the driving signal to a light-emitting device according to a light-emitting time control signal.

Display panel and pixel circuit thereof

A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.

Three dimensional gate structures with horizontal extensions

Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.

Verification algorithm for metal-oxide resistive memory

An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Stacked IC device with recessed conductive layers adjacent to interlevel conductors

A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element.

Nonvolatile stacked nand memory

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Hsinchu, Taiwan

Yan-Ru Chen