Saifun Semiconductors Ltd.

Other

Yan Polansky

Joseph Shor

Eduardo Maayan

Avi Lavan

Guy Cohen

A multi-level cell (MLC) memory array may be programmed using a programming circuit having a binary input register to store data to be input into the MLC array and a register to store a programming vector, where each element in the programming vector corresponds to a charge storage region of an MLC in the array. A controller may map pairs of bits from the input register to elements in the programming vector, such that mapping a pair of bits to an element of the programming vector may set the vector element to a 'program' value if the pair of bits corresponds to at least one specific program state associated with the programming vector.

Memory array programming circuit and a method for using the circuit

The present invention is a multi-phase method, circuit and system for programming non-volatile memory ('NVM') cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds a first intermediate voltage, and to cause a charge pump circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

Method, system and circuit for programming a non-volatile memory array

A multi-level cell (MLC) memory array may be programmed using a programming circuit having a binary input register to store data to be input into the MLC array and a register to store a programming vector, where each element in the programming vector corresponds to a charge storage region of an MLC in the array. A controller may map pairs of bits from the input register to elements in the programming vector such that mapping a pair of bits to an element of the programming vector may set the vector element to a 'program' value if the pair of bits corresponds to at least one specific program state associated with the programming vector.

A discharge device comprising a transistor configured as a source follower, a capacitance load to be discharged connected via a switch to a source terminal of the source follower, a reference voltage connected to a gate terminal of the source follower, and a current load element connected to a drain terminal of the source follower.

Fast discharge for program and verification

A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

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Ramat Gan, Israel

Yan Polansky