Globalfoundries Inc.

Yan Ping Shen

Haiting Wang

Min-Hwa Chi

Wei Hua Tong

Seung Yeon Kim

Tien-Ying Luo

Feng Zhou

Haoran Shi

Jin Ping Liu

Jun Lian

Xusheng Kevin Wu

Yong Meng Lee

Ashish Kumar Jha

Weihua Tong

Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Conformal nitridation of one or more fin-type transistor layers

A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting Nin the first Ti layer vertically at a 0&#xb0; implant angle in the pFET RMG trench; annealing the Nimplanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0&#xb0;; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology

Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Fabricating transistor(s) with raised active regions having angled upper surfaces

A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Forming a gate by depositing a thin barrier layer on a titanium nitride cap

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Saratoga Springs, NY, United States of America

Yan Ping Shen