Sandisk Corporation

Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk 3d LLC

Sandisk Il Ltd.

Other

Kabushiki Kaisha Toshiba

Sandisk Enterprise IP LLC

Sandisk Ii, Ltd.

Yan Li

Jian Feng Chen

Jeffrey W Lutze

Raul-Adrian Cernea

Steven Theodore Sprouse

Yupin K Fong

Siu Lung Chan

Eran Sharon

Idan Alrod

Alon Marcu

Tai-Yuan Tseng

Deepanshu Dutta

Nima Mokhlesi

Seungpil Lee

Teruhiko Kamei

Shahzad Khalid

Masaaki Higashitani

Farookh Moogat

Hiroyuki Mizukoshi

Luca Giovanni Fasoli

Toru Miwa

Kwang-Ho Kim

Yuheng Zhang

Johann Alsmeier

Tz-Yi Liu

Yacov Duzly

Mehrdad Mofidi

Loc Tu

Emilio Yero

Charles Moana Hook

Tomoharu Tanaka

Yanli Zhang

Dana Lee

Jun Wan

Grishma Shah

Jixin Yu

Gopinath Balakrishnan

Alex Mak

Sergey Anatolievich Gorobets

Mohan Dunga

Dejan Vucinic

Hadas Oshinsky

Khandker N Quader

Bo Liu

Cynthia Hsu

Chao Sun

Long C Pham

Gokul Kumar

Vijay Chinchole

Yingda Dong

Hem P Takiar

Hiroyuki Ogawa

Nian Niles Yang

Daniel C Guterman

Xiang Yang

Gerrit Jan Hemink

Man Lung Mui

Liang Li

George Samachisa

Tianhong Yan

Fumiaki Toyama

Raul Adrian Cernea

Akio Nishida

Tien-Chien Kuo

Jason T Lin

Chi-Ming Wang

Daxin Mao

Zhenyu Lu

Kazunori Kanebako

Johann George

Pao-Ling Koh

Alexander Kwok-Tung Mak

Eugene Jinglun Tam

Fanglin Zhang

Kenneth Louie

Min She

Alexander K Mak

Nitin Kumar Gupta

Alexander Bazarsky

Toshiki Hirano

Ran Zamir

Ken Oowada

Aaron Keith Olbrich

Zhixin Cui

Anubhav Khandelwal

Deepak Raghu

Jonathan Huynh

Yuki Mizutani

Po-Shen Lai

Philip David Reusswig

Shiv Harit Mathur

Jongmin Park

Ohwon Kwon

Kensuke Yamaguchi

Vinayak Ashok Ghatawade

Anirudh Amarnath

Xuan Tian

Ramakrishnan Subramanian

Chun Ge

Masakazu Ehama

Devices and methods to implement semantic searching on SSD through a computational SSD system that distributes computing to each NAND flash die of the SSD while the SSD controller handles the results aggregation with new on-die computation logic circuits to provide on device file semantic search are disclosed herein. The computational SSD system can read file feature vectors from multiple dies to the SSD controller, and if needed, these feature vectors may be buffered in DRAM and controller handles distance computing. Local, on-die AI/ML processing units may perform, for example, computation and comparison operations and pass the processing scores and results to the SSD controller. The SSD controller aggregates results from all dies and returns the result to the host. The feature vector store size, circuitry and number of on-die AI/ML processing units may be configured as needed to adapt to different tasks, system constraints, and/or feature vector sizes.

Error correction methods for computational SSD supporting rapid file semantic search

A data storage device is configured to store a database of objects in an NVM die as binary vectors and to then search the database based on binary key vectors. The binary vectors may be received from a host for storage in the NVM die. In other examples, a data storage controller converts floating-point vectors received from the host into binary vectors for storage in the NVM die. Various procedures are described for converting the floating-point vectors into binary vectors. Exemplary procedures are also described for comparing a binary key vector received from the host with the binary vectors stored in the NVM die to detect matches. For example, a sequence of commands is described for applying by the data storage controller to the NVM die to control the die to identify and count matching bits using the latches of the NVM die. Volatile memory implementations are also described.

Memory die with on-chip binary vector database search

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

Compute in memory three-dimensional non-volatile nor memory for neural networks

A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.

Configurable capacitors with 3D non-volatile array

Technology is disclosed herein for detecting leaky word lines in a non-volatile storage system. The exact leaky word line may be located very rapidly using a divide and conquer approach. First a determination may be made whether at least one word line in a group such as any of the word lines in a block is leaky. This initial determination can be made very quickly. If no word line in the group is leaky, the search can end. However, responsive to a determination that at least one word line in the group is leaky, a divide and conquer search may be performed in which the group of the word lines is repeatedly divided into smaller sub-groups with selected smaller sub-groups tested for a short circuit until the leaky word line is located.

Fast search for leaky word line

Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

Simulating memory cell sensing for testing sensing circuitry

An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.

Soft data compression for non-volatile memory

In some implementations, the present disclosure relates to a method. The method includes obtaining a set of weights for a neural network comprising a plurality of nodes and a plurality of connections between the plurality of nodes. The method also includes identifying a first subset of weights and a second subset of weights based on the set of weights. The first subset of weights comprises weights that used by the neural network. The second subset of weights comprises weights that are prunable. The method further includes storing the first subset of weights in a first portion of a memory. A first error correction code is used for the first portion of the memory. The method further includes storing the second subset of weights in a second portion of the memory. A second error correction code is used for the second portion of the memory. The second error correction code is weaker than the first error correction code.

Optimized neural network data organization

A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.

Pipelined micro controller unit

An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

Pre-computation of memory core control signals

A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Dynamic re-evaluation of parameters for non-volatile memory using microcontroller

A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

Fixed size soft bit lossy compression in flash memory

A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

CAM storage schemes and CAM read operations for detecting matching keys with bit errors

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Microcontroller architecture for non-volatile memory

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Milpitas, CA, United States of America

Yan Li