National Cheng-Kung University

National Science Council

National Science Council of Republic of China

National Science Council of R.o.c.

Epitech Corporation, Ltd.

Yan-Kuin Su

Chun-Liang Lin

Kuan-Chun Chen

Shi-Ming Chen

Shoou-Jinn Chang

Jin-Quan Huang

Shu-Kai Hu

Chih-Yuan Huang

Chin-Yao Tsai

Wen-Liang Li

Wen-Bin Chen

Wen-Rui Chen

James E Morris

Chuing-Liang Lin

Chin Yao Tsai

Shoou Jinn Chang

A method for manufacturing a heat dissipation bulk of a semiconductor device including the following steps is described. An electrically conductive layer is formed to cover a surface of a temporary substrate. At least one semiconductor chip is connected to the electrically conductive layer by at least one metal bump, wherein the at least one metal bump is located between the at least one semiconductor chip and the electrically conductive layer. A metal substrate is formed on the electrically conductive layer, wherein the metal substrate fills up a gap between the at least one semiconductor chip and the electrically conductive layer. The temporary substrate is removed.

Method for manufacturing heat dissipation bulk of semiconductor device

An embedded metal heat sink for a semiconductor device is described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit.

Embedded metal heat sink for semiconductor

An embedded metal heat sink for a semiconductor device and a method for manufacturing the same are described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit.

Embedded metal heat sink for semiconductor device and method for manufacturing the same

A method for manufacturing a heat sink of a semiconductor device is described. In the method, an adhesive tape is provided, wherein the adhesive tape includes a first surface and a second surface on opposite sides, and the first surface of the adhesive tape adheres to a surface of a temporary substrate. At least one semiconductor device is provided, wherein the semiconductor device includes a first side and a second side opposite to the first side, and the first side of the one semiconductor device is pressed and set into a portion of the second surface of the adhesive tape, and the second side of the one semiconductor device is exposed. A thin metal layer is formed on the second side of the semiconductor device and the exposed portion of the second surface of the adhesive tape. A metal heat sink is formed on the thin metal layer. Then, the adhesive tape and the temporary substrate are removed.

Method for manufacturing heat sink of semiconductor device

A lateral current blocking light emitting diode (LED) and a method of making the same are disclosed. The present invention features in that a trench is formed between the two electrodes via the technique of such as etching, wherein the depth of the trench reaches to at least the active layer, thereby blocking the lateral current between the two electrodes. With the use of the present invention, the possibility of the current passing through the active layer can be increased, thereby improving the brightness of the LED; and the chance of the photons emitted from the lateral of the trench can be raised wherein the photons are generated from the active layer, thereby increasing the output efficiency of the photons generated from the active layer.

Lateral current blocking light emitting diode and method of making the same

An ohmic contact to II-VI compound semiconductor device for lowering the contact resistance and increasing the efficiency and reliability of a photoelectric device. The method of manufacturing the ohmic contact to a II-VI compound semiconductor device comprises the steps of forming a II-VI compound semiconductor layer on the substrate, forming a mask layer with a contact via on the II-VI compound semiconductor layer, forming a metal-contact layer on the mask layer and II-VI compound semiconductor layer, and removing the metal-contact layer over the mask layer, wherein the remainder of the metal-contact layer forms the ohmic contact. In order to prevent oxidization of the metal-contact layer, a shield layer comprised of a noble metal can be disposed on the metal-contact layer.

Ohmic contact to a II-VI compound semiconductor device and a method of manufacturing the same

A InGaSb/GaSb strained-layer superlattices infrared photodetector in which the light-hole and heavy-hole are dispersed by the stress of the lattice mismatch, making the confined energy of the light hole and that of the heavy hole different. The wave function coupling of 1C-1HH is larger at near zero bias, thus the 1C-1HH is dominant. The wave function coupling of 1C-1LH is increased as reverse bias increases. When the reverse bias is high enough, the 1C-1HH transition becomes dominant. Because the transition energy of 1C-1HH and that of 1C-1LH are different, the modes of photodetector can be modulated by applying voltage.

Two-mode InGaSb/GaSb strained-layer superlattice infrared photodetector

The invention concerns an InAs/GaSb superlattice infrared detector that is prepared on a GaSb or a GaAs substrate by low pressure organometaleic chemical vapor deposition. The thickness of well and barrier modulated in the superlattice is used to control the wavelength of absorption. As the superlattice is sandwiched by the Si-doped InAs layer, the wavelength of absorption is in the 8.about.14 .mu.m range. As the superlattice is sandwiched by the Zn-doped GaSb layer, the wavelength of absorption is in the 3.about.5 .mu.m range.

InAs/GaSb superlattice structure infrared detector fabricated by

This invention is a new type of GaInP/AlGaInP for a visible separate-confinement-heterostructure strained quantum well(SCH-S-QW) laser with passive wave guides in the cladding layers. By using this structure, we can significantly improve the transverse beam divergence with only a slight increase of the threshold current. With proper choice of parameters, the transverse beam divergence as narrow as 18.degree.. FWHM can be achieved while the threshold current only becomes 1.12 factor than the lasers without the passive waveguide structure. This type of structure has three advantages:

Red semiconductor laser of low beam divergence

The present invention is related to a high efficiency indium gallium phosphide NIP solar cell, wherein an intrinsic layer between a emitter layer and base layer can suppress the Zn memory effect and interdiffusion and also a higher doping concentration in n-type AlInP window layer can be attained and the lifetime of minority carriers also increase for improving the conversion efficiency, thus the present invention may be used in the superhigh efficiency tandom cell so as to be used in the space or in earth as an regenerated energy.

High efficiency GaInP NIP solar cells

In a method for producing a semiconductor device using a logic simulation approach, a circuit model for a user-specified design of a multi-peak resonant tunneling diode-based electronic circuit is provided and includes a plurality of circuit devices. One of the circuit devices is a multi-peak resonant tunneling diode which is modeled by a parasitic resistance in series with parallel combination of a voltage-controlled current source and an intrinsic capacitance. The voltage-controlled current source has an equivalent circuit model with a function stage for realizing current-voltage characteristic curve of the resonant tunneling diode. The function stage includes parallel combination of at least one first circuit branch, at least one second circuit branch and a third circuit branch. Each of the first and second circuit branches has a resistor, a diode and a voltage source. The third circuit branch has a resistor and a voltage source. The first and third circuit branches represent positive resistance sections, and the second and third circuit branches represent negative resistance sections of the current-voltage characteristic curve.

Growing community of inventors

Tainan, Taiwan

Yan-Kuin Su