United Microelectronics Corp.

Yan-Hsiu Liu

Wei-Lun Hsu

Ji-Fu Kung

Ming-Tsung Yeh

Yao-Pi Hsu

Yung-Chien Kung

Am-Tay Luy

An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Integrated circuit structure with semiconductor devices and method of fabricating the same

A method of fabricating multilevel interconnects includes providing a substrate having a pixel array area and a logical circuit area, forming a first dielectric layer on the substrate, performing a first metallizing process on the first dielectric layer to form a first patterned metal layer and a second patterned metal layer above the pixel array area and the logical circuit area respectively, forming a second dielectric layer on the first patterned metal layer, the second patterned metal layer, and the first dielectric layer, performing a second metallizing process on the second dielectric layer to form a third patterned metal layer and a fourth patterned metal layer above the pixel array area and the logical circuit area respectively, wherein patterns of the fourth and the second patterned metal layer interlace to completely cover the logical circuit area, and depositing a dielectric layer on the third and the fourth patterned metal layer.

Multilevel interconnects structure with shielding function and fabricating method thereof

A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Next, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.

Integrated circuit structure including schottky diode and method for manufacturing the same

A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A number of circuit units are then formed in the internal region on the substrate. Thereafter, a dielectric layer is formed over the substrate, interconnects are formed in the dielectric layer within the internal region, and a number of bonding pad structures are formed in the dielectric layer within the external region. Finally, a cutting process is performed along a number of scribed lines on the substrate to form a number of chips. The bonding pad structures are exposed at the sides of each chip.

Method of fabricating intergrated circuit chip

A method of fabricating an LCoS display with a color pixel array comprises a step of disposing reflective layers between various color filter layers. The reflective layers are used as etching stop layers between color filter layers so that etching processes are capable of defining patterns of the color filter layers in different sub-pixels for forming the color pixel array.

Growing community of inventors

Tainan, Taiwan

Yan-Hsiu Liu