Semiconductor Manufacturing International (Shanghai) Corporation

Semiconductor Manufacturing International (Beijing) Corporation

Semiconductor Manufacturing (Shanghai) International Corporation

Semiconductor Manufacturing (Beijing) International Corporation

Semiconductor Manufacturing International Corp.

Yan Geng

Yan Chen

Kai Zhu

Yan Ling

Xiao Yuan Ma

The present disclosure provides an IO circuit and an access control signal generation circuit for the IO circuit. In one implementation, the access control signal generation circuit includes: a bias module coupled with an IO port, for generating an access control signal according to an IO port signal and an IO control signal, where a voltage value of the access control signal is a maximum value of a voltage value of an IO port voltage division signal and a voltage value of the IO control signal, and the voltage value of the IO port voltage division signal is a percentage of a voltage value of the IO port signal; an access control module coupled with the bias module, the access control module configured to control cut-off or conduction when receiving the access control signal and the IO port signal and outputting a first interface signal; and a higher-selection module configured to generate a second interface signal according to an IO power source signal and the IO port signal. In the present disclosure, the voltage of the first interface signal varies according to the voltage of an IO port, so as to resolve the problem of reliability, thereby improving the open-drain performance.

IO circuit and access control signal generation circuit for IO circuit

A receiver includes a first transfer gate, a first inverter, a second inverter, a second transfer gate, a third inverter, and a fourth inverter connected in series, a first power supply supplying power to the first and second inverters, a second power supply supplying power to the third and fourth inverters, a third power supply supplying power to the second transfer gate, first and second signals having opposite logic levels for controlling the first transfer gate. The third power supply is significantly lower than the first or second power supply. The leakage current of the receiver is significantly reduced in the core when the second power supply remains on but the first power supply is turned off while the performance of the receiver remains the same.

Low core power leakage structure in IO receiver during IO power down

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Shanghai, China

Yan Geng