Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Yan Dumchin

Yuri Ryabinin

Eran Sharon

Idan Alrod

Ran Zamir

Ishai Ilani

Idan Goldenberg

Yair Baram

Mark Fiterman

Eran Banani

Yuval Yoskovits

Shay Benisty

Alexander Bazarsky

Ariel Navon

Dudy David Avraham

Omer Fainzilber

Tal Sharifie

Leonid Minz

Michael Tomashev

Mark Naumenko

Alexander Mostovoy

Yevgeny Kaplan

Suzanna Zilberman

Igal Mariasin

Tzvi Alon

Yoav Porat

A storage device includes multiple memory dies and a controller configured to: (i) encrypt a data block using a key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block; (ii) during the encrypting, modify a key register during a first plurality of iterations, the key register being updated to a final state of the key register after a final iteration of the plurality of iterations; (iii) store the final state of the key register as a decryption key; and (iv) decrypt the encrypted data block using another key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.

Low latency block cipher in memory devices

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Data storage device with efficient decoder pool and method for on-the-fly decoder initialization

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to decode data from the memory device, store a decoder level for the decoded data in a bloom filter, receive a read command for the data, and decode the data using a decoder associated with the stored decoder level. The decoder level corresponds to a decoder having a certain decoding strength. The decoder level is stored in the bloom filter as an ID, where a bloom filter may be associated with each decoder level.

Optimizing recovery of recurrent blocks using bloom filter

A data storage device includes two or more memory devices and a controller coupled to the two or more memory devices. The controller is configured to program data to one or more memory devices of the two or more memory devices, select one or more of the one or more memory devices to have additional ECC for the data of the one or more memory devices, program the additional ECC to a first memory device. The data is programmed with error correction code (ECC). The first memory device is distinct from the one or more memory devices. The first memory device is disposed in a central module, where the central module includes additional decoding capability. The additional ECC and the corresponding data with ECC are concatenated and decoded for additional error correction capability.

Centralized SRAM error location detection and recovery mechanism

An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.

Decoder for irregular error correcting codes

A device includes a non-volatile memory and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit coupled to the DPUs. The control circuit is responsive to an error metric associated with the representation of the codeword and is configured to set a message resolution at least partially based on the error metric and to selectively disable one or more components of the LDPC decoder based on the message resolution.

ECC decoder with selective component disabling based on decoding message resolution

A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.

Configurable ECC decoder

A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

ECC decoder with multiple decoding modes

A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.

Storage device operations based on bit error rate (BER) estimate

A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.

A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.

Virtual critical path (VCP) system and associated methods

A storage system may include a queue included in a memory and a controller configured to store commands received from a host in the queue. The queue may have a linked-list configuration. In response to a triggering event, the controller may take a snapshot of the queue, creating a snapshot queue. The snapshot queue may have a linear configuration. Subsequent analysis or parsing of queued information may be performed on the linear snapshot queue instead of the linked-list queue. Modifications to the linear snapshot queue may be corresponding made to the linked-list queue.

Storage systems that create snapshot queues

A system and method for encrypting and/or decrypting data with a Cryptomeria (C2) cipher may be provided that generates C2 round keys in parallel. Accordingly, data may be encrypted or decrypted at least twice as fast as without the system. A storage device may encrypt data written to the storage device and/or decrypt data read from the storage device with such a system.

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Beer Sheva, Israel

Yan Dumchin