Future Wei Technologies, Inc.

Huawei Technologies Co., Limited

Yan Duan

Shou-Po Shih

Gong Tom Lei

Liang Gu

Yuming Cao

Yen Dang

Yifan Gu

Hungyi Lee

Mamatha Deshpande

Gong Lei

An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Reference-less frequency detector with high jitter tolerance

A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

Interference-immunized multiplexer

An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.

Combined low and high frequency continuous-time linear equalizers

An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (&#x3a9;).

On-chip test interface for voltage-mode Mach-Zehnder modulator driver

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Ames, IA, United States of America

Yan Duan