United Microelectronics Corp.

Yan-Chun Chen

Ming-Jui Chen

Te-Hsien Hsieh

Jing-Yi Lee

Cheng-Te Wang

Ping-I Hsieh

Shih-Ming Kuo

Jian-Yuan Ma

The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.

Pattern verifying method

A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Method for optimizing an integrated circuit layout design

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Kaohsiung, Taiwan

Yan-Chun Chen