Dsp Semiconductors Ltd.

Dsp Semiconductors USA, Inc.

Yakov Milstein

Yael Gross

Bat-Sheva Ovadia

Ronen Perets

Yair Be'ery

Gideon Wertheizer

A data processing and addressing unit for processing a set of either first or second type instructions having associated therewith operands stored in a single memory bank and operands stored in two memory banks, respectively. First and second memory banks are mapped in continuous memory address space such that a bottom address of the second memory bank is contiguous with a top address of the first memory bank. A method is employed for mapping the first and second memory banks so as to permit memory expansion or contraction while permitting the first and second memory banks to be configured as a single continuous buffer or as two distinct buffers, as required. According to the method, the first memory bank is mapped as a negative offset with respect to the bottom address of the second memory bank such that the top address of the first memory bank has an offset of -1 and a bottom address thereof has an offset of -(first size); and the second memory bank is mapped as a positive offset with respect to the bottom address of the second memory bank such that a top address thereof has an offset of (second size - 1). Expansion or contraction of the first and second memory banks may thus be effected relative to a common boundary between the two memory banks and independent of their respective sizes.

Expandable memory for a digital signal processor including mapped first

An improved cyclical buffer having an integer M number of memory locations in respect of which a number STEP of consecutive memory locations are required to be accessed in a single operation and having a predetermined START location defining an initial memory location to be accessed. M is constrained to be an integer multiple of STEP and the k least significant bits of START are zero where k is the minimal integer satisfying the relation 2.sup.k &gt;M-.vertline.STEP.vertline.. The result is the same as the general MODULO algorithm employed in conventional cyclical buffers but without the cost of implementing the complete MODULO function. An apparatus for generating successive addresses involves an ADDER and a k-bit COMPARATOR coupled via a MULTIPLEXER to an address register such that the k-least significant bits of the ADDER or M-.vertline.STEP.vertline. or 0 is fed to the k-least significant bits of the address register depending on the output of the k-bit COMPARATOR.

Simplified cyclical buffer

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Natanya, Israel

Yakov Milstein