Intel Corporation

Proteantecs Ltd.

Tahoe Research, Ltd.

Yair Talker

Eyal Fayneh

Evelyn Landman

Shai Cohen

Yahel David

Inbar Falkov

Inbar Weintrob

Inder M Sodhi

Tapan A Ganpule

Elias Nassar

Tanveer R Khondker

Vijay K Vuppaladadium

Ramkumar Krithivasan

Miguel A Corvacho Hernandez

Alexander Gendler

Samer Nassar

Arye Albahari

Yossi Ben Simon

Samer Nasser

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Integrated circuit profiling and anomaly detection

A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

Efficient integrated circuit simulation and testing

A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems

In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.

Dyanamically adapting a voltage of a clock generation circuit

Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a hardware logic unit, of the multiple hardware logic units, in response to a logic level of the enable signal, wherein the clock islands are part of a global clock distribution network and are operable to be enabled or disabled independently.

Apparatus, system, and method for providing clock signal on demand

Growing community of inventors

Binyamina, Israel

Yair Talker