Panasonic Avionics Corporation

Intel Corporation

Yair Shemesh

Paul Anthony Margis

Tzvi Maimon

Benjamin Engel

Brinder Bhatia

David Levy

Michael Sigalov

Amir Haber

Shai Gross

An antenna assembly including a support and antenna tiles disposed in the support. The antenna tiles form an external surface corresponding substantially in shape to lateral faces of a frustum. The frustum includes a central axis with the antenna tiles disposed around the central axis of the frustum and sloping away therefrom. Each antenna tile includes opposite ends, with one end narrower than the other end. A planar array of antenna elements is disposed on each antenna tile in which the antenna elements of each array are configured to operate as a phased array. A control system connects to the planar arrays of antenna elements in which the control system is configured to selectively activate and deactivate each of the planar arrays.

Antenna assembly

An antenna system is provided. The antenna system includes a planar array of antenna elements configured to operate as an array having a plurality of receive (Rx) antenna elements for receiving a signal in a first frequency band and a plurality of transmit (Tx) antenna elements for transmitting a signal in a second frequency band. The Rx antenna elements and the Tx antenna elements are interleaved in a pattern such that total Tx power leakage is distributed among the plurality of Rx antenna elements. Furthermore, each Rx antenna element is provided with a high dynamic range amplifier (HDRA) for amplifying a receive signal and filtering any Tx power leakage at each Rx antenna element.

Antenna system with high dynamic range amplifier for receive antenna elements

An integrated circuit may include a receiver and/or a transmitter that performs third order sub-harmonic conversion. The integrated circuit may include a Gilbert cell active mixer with three or more serially-connected transistors in each of the mixer's four branches. Alternatively, the integrated circuit may include a quad-ring passive resistive mixer with three or more serially-connected transistors in each of the mixer's four branches. Alternatively, the integrated circuit may include a logic circuit and a mixer. The logic circuit may apply logic operations to periodic logic signals having a local frequency and to delayed versions thereof to produce reference signals having a dominant spectral component at three times the local frequency. The mixer may mix input signals with the reference signals to produce output signals having a dominant spectral component at three times the local frequency less a center frequency of the input signals.

Integrated circuit and methods for third sub harmonic up conversion and down conversion of signals

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Haifa, Israel

Yair Shemesh