Lsi Corporation

Yair Orbach

Assaf Rachlevski

Nahum N Vishne

A circuit having a pipeline and a configuration circuit. The pipeline generally has multiple stages linked in series by registers. The registers may be governed by a clock signal having a first frequency in a first mode and a second frequency in a second mode. The second frequency may be slower than the first frequency. Each stage may have a respective one of multiple first latencies each shorter than a first period of the first frequency. The configuration circuit may be disposed in the pipeline. The configuration circuit generally bypassing selectively a particular register while in the second mode to form a combined stage. The combined stage may (i) comprise a first of the stages adjoining the particular register and a second of the stages adjoining the particular register and (ii) have a second latency shorter than a second period of the second frequency.

Variable length stages in a pipeline

An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.

Uninitialized memory detection using error correction codes and built-in self test

An apparatus having a memory and a controller is disclosed. The memory may be configured to (i) store a plurality of cache lines, each of the cache line comprising a plurality of locations including a respective end location and (ii) accessing a particular one of the cache lines identified by a cache address signal. The controller may be configured to (i) buffer a plurality of line pointers, each of the line pointers identifying a respective boundary one of the locations in one of the cache lines and (ii) generate the cache address signal in response to a processor address signal hitting a given one of the locations residing between the respective boundary location and the respective end location.

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Shomron, Israel

Yair Orbach