Globespan Virata Corporation

Globespan Semiconductor, Inc.

Yair Aizenberg

Yue-Peng Zheng

Daniel Amrany

Laurent Alloin

Peter Kleewein

Yong Je Lim

The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.

Apparatus and system for blocking memory access during DMA transfer

The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way. More particularly, after computing a first set of complex butterfly operations (each having the same twiddle value) in a given computation stage, a first complex butterfly operation (having a different twiddle value) of a second set of complex butterfly operations, is computed in that stage. Thereafter, all remaining complex butterfly operations (having the same value) in that stage will be computed. This methodology will be repeated until all butterfly operations are calculated in each stage. An addressing circuit is also provided for addressing a data memory in a system for computing a FFT, the system having a data memory for storing data values and a coefficient memory for storing coefficient values.

Method for computing a fast fourier transform and associated circuit for addressing a data memory

A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Circuit and method for computing a fast fourier transform

A process circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a date pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

The present invention is generally directed to a multi-mode buffer that is configurable to control output delivered to an input, with a variable clock cycle delay. For example, the buffer may be controlled, in one mode to deliver input data to an output, at a one clock cycle delay (i.e., output data at next clock edge). In another mode, the buffer may be controlled to deliver input data to an output, at a two clock cycle delay. In accordance with one aspect of the present invention, the buffer includes a clock input, a data input, a control input, and an output. The input and the output may be of variable bit width. For example, 8 bits, 16 bits, or some other bit width. The buffer further includes circuitry for delivering data on the data input to the output in response to the clock input. In this regard, the buffer includes circuitry responsive to the control input to vary a delay in delivering the data input to the output, such that the delay may be one clock cycle, two clock cycles, or some other desired length.

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Tinton Falls, NJ, United States of America

Yair Aizenberg