International Business Machines Corporation

Yabin Wang

Steven Michael Eustis

Peter Francis Croce

Robert L Barry

A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Complementary two transistor ROM cell

A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.

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Ithaca, NY, United States of America

Yabin Wang