Marvell Asia Pte., Ltd.

Yaakov Yehezkel

Adi Katz

Eliya Babitsky

Moran Noiman

Ofer Halili

Tal Robinson

A circuit and corresponding method perform timestamp filtering. The circuit includes recursive filter logic that implements a recursive least-squares (RLS) filter. The circuit (i) generates a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic applies the RLS filter to a portion of the received timestamp. A number of bits of the portion is less relative to a total number of bits of the received timestamp. The circuit outputs the filtered timestamp generated. Applying the RLS filter to the portion enables the circuit to be more efficient (e.g., smaller adders, fewer flipflops, etc.), thereby reducing area and power consumption of the circuit.

Circuit and method for timestamp filtering with RLS filter

A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.

Circuit and method for timestamp jitter reduction

A method of reducing jitter in transmission of a timestamp across a clock domain boundary includes storing N timestamps, generated in N successive clock cycles of an origin clock domain, in N parallel buffers in the origin clock domain under control of a modulo-N counter, transmitting outputs of the N parallel buffers across the clock domain boundary into a destination clock domain along with the modulo-N counter, processing the modulo-N counter in the destination clock domain to derive a selection signal that selects a stable timestamp from among the outputs of the N parallel buffers, and outputting the selected stable timestamp. The modulo-N counter may be Gray-coded modulo-N counter to reduce jitter in the modulo-N counter across the clock domain boundary.

Method and apparatus for passing clock signals between time domains

A circuit and corresponding method perform timestamp filtering. The circuit comprises input format-conversion logic that converts a received timestamp from an original timestamp format to an intermediate timestamp format. The circuit further comprises recursive filter logic coupled to the input format-conversion logic. The recursive filter logic generates a filtered timestamp in the intermediate timestamp format by filtering the received timestamp in the intermediate timestamp format. The circuit further comprises output format-conversion logic coupled to the recursive filter logic. The output format-conversion logic converts the filtered timestamp from the intermediate timestamp format to the original timestamp format and outputs the filtered timestamp in the original timestamp format. Converting the received timestamp into a different format avoids use of complex logic to handle rollover of input values, thereby reducing area and power consumption of the circuit.

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Rehovot, Israel

Yaakov Yehezkel