Intel Corporation

International Business Machines Corporation

Yaakov Yaari

Millind Mittal

Benny Eitan

Alexander D Peleg

Larry M Mennemeier

Derrick Chu Lin

Punit Minocha

Aharon Kupershtok

Moshe Klausner

Srinivas Chennupaty

Yousef Shajrawi

Nitzan Peleg

Andre Heilper

Rachel Tzoref

Uri C Weiser

Daniel Citron

Grigori Chtrasberg

David Perlmutter

Andre Heiper

A method, system and product for predicting an outcome of a program based on input. The method comprising: obtaining an input to be used by a program prior to executing the program; predicting by, a machine learning module, a predicted outcome of the program based on the input; wherein the predicted outcome is selected from the group consisting of: a pass outcome and a fail outcome, wherein the pass outcome is the program executing without failing when using the input, and wherein the fail outcome is the program failing when using the input.

Predicting outcome based on input

A method comprising: counting each occurrence of a hardware event by a Performance Monitoring Counter of a hardware processor during the execution of a target program code; orderly and continuously storing in a buffer of a Taken Branch Trace (TBT) Facility of said hardware processor a predefined TBT size of last taken branches of said target program code during its execution; every time said counting equals a sampling rate, triggering sampling of said buffer, to receive a TBT comprising current said predefined TBT size of last taken branches; constructing a full branch trace for each said TBT based on said target program code; extracting a predefined Chopped Branch Trace (CBT) size of last branches from each said full branch trace, to receive a chopped branch trace for said each TBT; and incrementally storing each said chopped branch trace to generate an edge profile of said target program code.

Hardware-based edge profiling

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Orderly storing of corresponding packed bytes from first and second source registers in result register

A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data elements, and a third register. A decoder to decode a packed instruction to identify the first and second registers as source registers and the third register as a destination register. And to decode a pack instruction to identify a fourth and a fifth register each having 16-bit data elements. At least one functional unit, responsive to the packed instruction, to store a result in the third register including only half of all data elements of each of the first and second registers, including only corresponding data elements from corresponding positions in the first and second registers, and responsive to the pack instruction to store a result that is to include an 8-bit data element for each 16-bit data element in the fourth and fifth registers.

Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements

Interleaving half of packed data elements of size specified in instruction and stored in two source registers

A processor of an aspect includes a register file including a first register to hold a first packed data including a first low data element and a first high data element, a second register to hold a second packed data including a second low data element and a second high data element, and a third register. The processor also includes a decoder to decode an unpack instruction. The processor also includes a functional unit coupled with the decoder and the register file. The functional unit, in response to the decoder decoding the unpack instruction, is to transfer the first low data element to a high position of the third register and the second low data element to a low position of the third register.

Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers

Processor executing unpack and pack instructions specifying two source packed data operands and saturation

Packing in destination register half of each element with saturation from two source packed data registers

Packing odd bytes from two source registers of packed data

Computer-implemented method, computerized apparatus and a computer program product for test selection. The computer-implemented method comprising: obtaining a test suite comprising a plurality of tests for a Software Under Test (SUT); and selecting a subset of the test suite, wherein the subset provides coverage of the SUT that correlates to a coverage by a workload of the SUT, wherein the workload defines a set of input events to the SUT thereby defining portions of the SUT that are to be invoked during execution.

Test selection

Packing lower half bits of signed data elements in two source registers in a destination register with saturation

Method and apparatus for unpacking and moving packed data

Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object.

Data object profiling during program execution

Packing signed word elements from two source registers to saturated signed byte elements in destination register

Detecting optimization opportunities is enabled by utilizing a trace of a target concurrent computer program and determining a relation between data objects accessed during the tracked execution. The relation may be stored in a Temporal Relation Graph (TRG), in an extended-TRG or another data structure. The relation may be affected by temporally-adjacent accesses to data objects. The relation may further be affected by accesses to data objects performed during critical sections of the target program.

Performance optimization based on data accesses during critical sections

Growing community of inventors

Haifa, Israel

Yaakov Yaari