Taiwan Semiconductor Manufacturing Comp. Ltd.

Ya-Yun Cheng

Chun Hsiung Tsai

Zhiqiang Wu

Chih-Hsin Ko

Yi-Ching Liu

Peng-Chun Liou

Sai-Hooi Yeong

Meng-Han Lin

Yu-Ming Lin

Clement Hsingjen Wann

Yen-Ming Chen

Carlos H Diaz

Wei-Yang Lee

Shahaji B More

I-Sheng Chen

Cheng-Yi Peng

Kuo-Feng Yu

Yi-Jing Lee

Wen-Hsing Hsieh

Jian-Hao Chen

Tzer-Min Shen

Hua Feng Chen

Chia-Ming Hsu

Hau-Yu Lin

Ting-Yun Wu

Sheng-Chen Wang

Hsueh-Chang Sung

Chih-Yu Chang

Tsung-Yao Wen

Hung-Wei Li

Wen-Ling Lu

Chung-Te Lin

Feng-Cheng Yang

Chia-En Huang

Mauricio Manfrini

Sheng-Chih Lai

Chun-Chieh Lu

Chia-Ta Yu

Chung-Wei Wu

Chen-Jun Wu

Yu-Chien Chiu

Chih-hsin Ko

Yu-chien Chiu

A ferroelectric memory device includes a multi-layer stack, a ferroelectric layer, and channel layers. The multi-layer stack is disposed on a substrate and includes conductive layers and dielectric layers stacked alternately. The ferroelectric layer has a curvy profile and is disposed along sidewalls of the conducive layers and sidewalls of the dielectric layers. The channel layers are separated from each other and disposed on the ferroelectric layer, and correspond to the conductive layers respectively.

Ferroelectric memory device and method of forming the same

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.

Semiconductor memory devices and methods of manufacturing thereof

A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.

Semiconductor memory devices with varying channel width and methods of manufacturing thereof

Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Ferroelectric device and methods of forming the same

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a gate, a ferroelectric layer disposed on the gate; a first channel layer disposed on the ferroelectric layer, a second channel layer disposed on the ferroelectric layer, and source and drain regions disposed on the first channel layer. The first channel layer includes a first thickness and the second channel layer includes a second thickness. A ratio of the first thickness and the second thickness is less than ⅗.

Source/drain engineering for ferroelectric field effect transistors

A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

Method for FinFET LDD doping

A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Memory array and operation method thereof

A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

Method of metal gate formation and structures formed by the same

Semiconductor memory devices with different thicknesses of word lines and methods of manufacturing thereof

A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.

A fin field device structure and method for forming the same are provided. The FinFET device structure includes a protruding structure extending from a substrate and an anti-punch through implant (APT) region formed in the protruding structure. The FinFET device structure includes a barrier layer formed on the APT region, and the barrier layer has a width in a horizontal direction. The width gradually tapers from a bottom of the barrier layer to a top of the barrier layer.

Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (finFET) device structure

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Taichung, Taiwan

Ya-Yun Cheng