United Microelectronics Corp.

Ya-Yin Hsiao

Chih-Chiang Wu

Tsai-Yu Wen

Ching-I Li

Ti-Bin Chen

Shi-You Liu

Huan-Chi Ma

Chien-Wen Yu

Shao-Ping Chen

Yu-Chun Liu

Yu-Ren Wang

Po-Jen Chuang

Ying-Wei Yen

Chia-Ming Kuo

Fu-Jung Chuang

Nan-Yuan Huang

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Semiconductor device and method for fabricating the same

A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

P-type field effect transistor and method for fabricating the same

A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

P-type field effect transistor having channel region with top portion and bottom portion

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Taipei, Taiwan

Ya-Yin Hsiao