Taiwan Semiconductor Manufacturing Comp. Ltd.

Ya-Wen Chiu

Lun-Kuang Tan

Yi Che Chan

Cheng-Po Chau

Szu-Ying Chen

Da-Yuan Lee

Hsien-Ming Lee

Yu-Sheng Wang

De-Wei Yu

Zheng-Yang Pan

Sen-Hong Syue

Hung-Yao Chen

Yi-Cheng Li

Chih-Hsiang Fan

Kun-Wa Kuok

Chih Ping Liao

Kai-Cyuan Yang

YungHao Wang

Jing-Huei Huang

Pin-Chu Liang

Yi-Hua Cheng

Pin-Ju Liang

In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Method of manufacturing a semiconductor device and a semiconductor device

In a method of manufacturing a semiconductor device, a source/drain structure is formed over a substrate, a first interlayer dielectric (ILD) layer including one or more dielectric layers is formed over the source/drain structure, a first opening is formed in the first ILD layer to at least partially expose the source/drain structure, a sacrificial layer is formed on an inner wall of the first opening, a first insulating layer is formed on the sacrificial layer, a conductive layer is formed on the first insulating layer so as to form a source/drain contact in contact with the source/drain structure, the sacrificial layer is removed to form a space between the first insulating layer and the first ILD layer, and a second insulating layer is formed over the source/drain contact and the first ILD layer to cap an upper opening the space, thereby forming an air gap.

Semiconductor device and manufacturing method thereof

A method includes forming a resist pattern over a structure, the resist pattern having a trench surrounded by first resist walls extending lengthwise along a first direction and second resist walls extending lengthwise along a second direction perpendicular to the first direction. The method includes loading the structure and the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction of the ion implanter. The method includes tilting the structure and the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method includes first rotating the structure and the resist pattern around the axis to a first position. The method includes first implanting ions into the resist pattern with the structure and the resist pattern at the first position.

Method for reducing line-end space in integrated circuit patterning

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Device and method for high pressure anneal

A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

Nitride-containing STI liner for SiGe channel

A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same

CMOS finFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same

A method includes forming a resist pattern, the resist pattern having trenches oriented lengthwise along a first direction and separated by resist walls along both the first direction and a second direction perpendicular to the first direction. The method further includes loading the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction, and tilting the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method further includes rotating the resist pattern around the axis to a first position; implanting ions into the resist walls with the resist pattern at the first position; rotating the resist pattern around the axis by 180 degrees to a second position; and implanting ions into the resist walls with the resist pattern at the second position.

In a method of manufacturing a semiconductor device, a source/drain structure is formed over a substrate, a first interlayer dielectric (ILD) layer including one or more dielectric layers is formed over the source/drain structure, a first opening is formed in the first ILD layer to at least partially expose the source/drain structure, a sacrificial layer is formed on an inner wall of the first opening, a first insulating layer is formed on the sacrificial layer, a conductive layer is formed on the first insulating layer so as to form a source/drain contact in contact with the source/drain structure, the sacrificial layer is removed to form a space between the first insulating layer and the first ILD layer, and a second insulating layer is formed over the source/drain contact and the first ILD layer to cap an upper opening of the space, thereby forming an air gap.

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Tainan, Taiwan

Ya-Wen Chiu