Au Optronics Corporation

United Microelectronics Corp.

National Chung Hsing University

Cambrios Film Solutions Corporation

Ya-Ting Lin

Tien-Hao Tang

Chun-Hsin Liu

Kun-Yueh Lin

Yu-Sheng Huang

Lu-An Chen

Chung-Hung Chen

Ting-Wei Guo

Kuan-Cheng Su

Chung-Chin Hsiao

Yu-Chung Yang

Wei-Chia Fang

Mei-Ling Chao

Chun-Hung Chu

Chun-Huan Chang

Yi-Chun Chen

Hou-Jen Chiu

Chun Huan Chang

Chun-Pin Fan

Shih-Ching Chen

Chen-Ju Liang

Yeh-Sheng Wang

A silver nanowire (SNW) protection layer structure includes a substrate; a SNW layer, disposed on the substrate and covering only a partial region of a surface of the substrate, the SNW layer including a plurality of SNW channels; and a SNW protection layer, disposed on the SNW layer and covering a region corresponding to the plurality of SNW channels, the SNW protection layer including a light-resistant antioxidant. A manufacturing method for the SNW protection layer structure above is further provided. The SNW protection layer structure and the manufacturing method thereof are applicable in a touch sensor.

Silver nanowire protection layer structure and manufacturing method thereof

An electronic device, including an antenna, includes a pixel array, a control circuit, and a gate driver. The control circuit is coupled with the antenna, and configured to receive a RF signal from the antenna. The gate driver is coupled with the control circuit and the pixel array, and includes multiple shift registers. Each of the multiple shift registers is configured to output a scan signal to the pixel array. The control circuit is configured to output a triggering signal to a first-stage shift register of the multiple shift registers. When the control circuit receives the RF signal, the triggering signal has a triggering pulse. When the first-stage shift register receives the triggering pulse, the first-stage shift register outputs the scan signal having an enabling voltage level.

Electronic device and driving method thereof

A display system includes a pixel array, an antenna, a reader circuit, and a gate driver circuit. The antenna is configured to transmit a radio frequency (RF) signal in response to a wireless communication. The reader circuit is coupled to the antenna and is configured to receive the RF signal. The gate driver circuit is coupled to the reader circuit and the pixel array. The reader circuit is further configured to generate a clock signal according to the RF signal and transmit the clock signal to the gate drive circuit. The gate driver circuit is configured to generate scanning signals according to the clock signal and transmit the scanning signals to the pixel array.

Display system

A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

Semiconductor device

A display panel includes a display area first and second gate line driving circuits. The display area includes a plurality of pixels is configured to determine how to process a data transmitted on a data line according to first and second control signals transmitted on first and second gate lines respectively and a second control signal transmitted on a second gate line and determine when to emit light according to a light emitting control signal transmitted on a light emitting control line. The first gate line driving circuit is coupled to the first gate line and for providing the first control signal thereto. The second gate line driving circuit is coupled to the second gate line and the light emitting control line and configured to provide the second control signal and the light emitting control signal thereto, respectively.

Display panel of combining gate control signal and emitting control signal

An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

Electrostatic discharge protection device with parasitic bipolar junction transistors

Display panel

An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.

Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise

A display panel includes a control circuit and a pixel structure. The control circuit selectively provides a data signal or a first reference voltage signal. The pixel structure includes a capacitor, a first, a second and a third switch unit. For the first switch unit, a first and a second terminal are coupled to two the capacitor in series, and a control terminal receives a control signal. For the second switch unit, a first terminal is coupled to the second terminal of the first switch unit, and the control terminal receives a first scan signal. For the third switch unit, a first terminal receives the data or first reference voltage signal, a second terminal is coupled to the second terminal of the second switch unit and a light emitting element, and the control terminal is coupled to the second terminal of the first switch unit.

Display panel and driving method thereof

A process for treating halide contaminated waste includes bringing the contaminated waste into contact with a reductone in an aqueous solution to obtain a mixture having a pH value, and adjusting the pH value to permit dissociation of two hydrogen ions from an enediol group of the reductone and to permit subsequent reaction of the reductone with an electrophilic site of halide contained in the contaminated waste. Halide can thus be removed.

Process for treating halide contaminated waste

An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region.

A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

Bus-line arrangement in a gate driver

A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

Display apparatus and method for generating gate signal thereof

A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

Growing community of inventors

Yunlin County, Taiwan

Ya-Ting Lin