United Microelectronics Corp.

Ya-Nan Mou

Chung-Cheng Tsai

Hsin-Pang Lu

Yuan-Hui Chen

Shi-Wen Chen

Yu-Yee Liow

Wen-Hong Hsu

Po-Hua Chen

Hsueh-Chen Cheng

Cheng-Hsiao Lai

Chung-Hao Chen

Ying-Ting Lin

Chi-Hsiu Hsu

Tsun-Lai Hsu

Shih-Chin Lin

Hsin-Wen Chen

Yung-Hsiang Lin

Chien-Liang Chen

Chi-Chang Shuai

Hsi-Wen Chen

Yu-Jen Chang

Zih-Yu Chiu

Chi-Fa Lien

Chien-Chung Pan

Chai-Wei Fu

Yu-Chin Tai

Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Anti-fuse memory

An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

Static random access memory

A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

Read only memory

A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

Voltage regulating circuit

An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Integrated circuit and signal monitoring method thereof

A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.

Non-volatile memory which can increase the operation window

A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.

Phase-locked loop and method for controlling the same

An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N&#x2212;M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N&#x2212;M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.

Memory and operation method thereof

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Memory for a voltage regulator circuit

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Operation method of a supply voltage generation circuit used for a memory array

A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array

A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.

Charge pump circuit with low clock feed-through

A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.

Capacitor structure

The integrated circuits array with latch up protection includes an active array and a guard array. The active array contains a plurality of integrated circuits devices having operational functions. The guard array abutting an outer peripheral portion of the active array contains a plurality of transistors for protecting the plurality of integrated circuits devices from latch up. In general, the active array can be functional circuits like a memory array or a read only memory (ROM) array. The plurality of transistors in the guard array can be formed simultaneously with transistors in the active array and have same structure with the transistors.

Latch up protection and yield improvement device for IC array

The input and output interface in the present invention can includes following components. A first circuit and a second circuit are placed. Means for switching a coupling between the two circuits is used. Grounding means is employed for setting the first terminal to a ground connection. Triggering means is used for triggering the grounding means and the switching means. The method for interfacing input and output between a first circuit and a second circuit includes the steps as follows. At first, an output disable signal of the first circuit is detected. Then a first terminal is isolated from a second terminal. The first terminal is an input and output terminal of the first circuit and the second terminal is an input and output terminal of the second circuit. Next, the first terminal is grounded. The first terminal is then floated. Finally, the first terminal and the second terminal is coupled for the first circuit to receive an output signal from the second circuit.

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Hsinchu, Taiwan

Ya-Nan Mou