Macronix International Co., Ltd.

Powerchip Technology Corporation

Ya-Jui Lee

Kuan-Fu Chen

Che-Ping Chen

Ying-Chia Lin

Shin-Jang Shen

Yih-Shan Yang

Atsuhiro Suzuki

Chen Wang

An operation method of a memory device including the following operations is provided. Applying a read voltage to a selected page of a plurality of programmed memory pages. Applying a first pass voltage to unselected pages of the plurality of programmed memory pages. Applying a second pass voltage to at least one unprogrammed memory page, wherein the first pass voltage is larger than the second pass voltage. A memory system including a 3D NAND flash memory with high capacity and high performance is also provided.

Operating method of memory device and memory system

A memory device and an operating method for the memory device are provided. The memory device includes a memory array and a control circuit. The memory array includes memory blocks. Each of the memory blocks is, for example a three-dimensional NAND flash memory block. The memory device provides a storage media with high-performance and high-capacity. The control circuit provides a first erasing voltage to perform a first erasing operation on target memory cell strings of a selected memory block in the memory blocks, performs a programming operation on the target memory cell strings after the first erasing operation, and provides a second erasing voltage to perform a second erasing operation on at least one part of memory cells of each of the target memory cell strings after the programming operation. The second erasing voltage is lower than the first erasing voltage.

Memory device and operating method for memory device

A method of programming a memory includes performing a plurality of programming shots is provided. Each programming shot includes a pre-charge stage and a programming stage and includes the following steps. Applying a common source line voltage to a common source line or applying a bit line voltage to a bit line in the pre-charge stage, wherein the common source line voltage or the bit line voltage is applied by using incremental-step-pulse programming (ISSP) in the plurality of pre-charge stages. Applying a programming voltage to a selected word line in the programming stage, wherein the programming voltage is applied by using ISSP in the plurality of programming stages.

Method of programming memory

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.

Memory programming operation comprising preprogramming memory cells

A memory device and programming method thereof are provided. A memory cell array includes a first dummy word line set, plural word lines and a second dummy word line set in sequence. The method includes: grouping the word lines into word line groups; generating at least one pass bias set having plural pass biases that are respectively corresponding to each word line group; selecting one word line for programming, and determining that the selected word line belongs to a specific word line group; and according to a programming sequence, applying a corresponding pass bias in the plural pass biases of the at least one pass bias set to at least one dummy word line in one of the first and the second dummy word line sets, wherein the corresponding pass bias corresponds to the specific word line group.

Memory device and programming method thereof

A flash memory and an erase method thereof are provided. The flash memory includes at least a memory array and a memory control circuit. The memory control circuit biases plural word lines, a common source line and a global bit line included in the memory array to erase plural memory cells in the flash memory. The method comprises grouping the plural word lines into plural word line groups according to erase depths corresponding to each word line; generating an erase voltage and plural multiple-step word line erase voltages; applying the erase voltage from at least one of the common source line and the global bit line; and during a period when the erase voltage is applied, the plural multiple-step word line erase voltages is respectively applied to the plural word line groups, wherein the plural multiple-step word line erase voltages is one-by-one corresponding to the plural word line groups.

Flash memory and erase method thereof

A method for programming a memory device and a memory system are provided, wherein the method for programming the memory device includes steps below. First, a program command is proposed. Second, a width of a pulse about to provide to strings of memory cells of the memory device is determined according to a temperature data of the memory device. Then, the pulse is provided to the strings of memory cells to start doing a program operation. The width of the pulse becomes narrower as a temperature of the memory device is raised.

Method for programming flash memory device and flash memory system

A memory device and a reading method thereof are provided. During a second reading period, a second bit line voltage is provided to a bit line having a read finished memory cell. Thus, a voltage difference between a bit line voltage and a pass voltage of memory cells on unselected word lines is reduced. A data value stored in the memory cells on a selected word line is determined according to whether the memory cells on the selected word line enter a preset state during a first reading period and the second reading period.

Memory device and reading method

A flash memory and an operation method thereof are provided. The flash memory includes a plurality of memory cell strings and a pass voltage generator. Each of the memory cell strings includes a plurality of memory cells. The pass voltage generator is configured to provide a pass voltage to a plurality of word lines of a plurality of unselected memory cells of a selected memory string. During a reading operation, the pass voltage generator raises the pass voltage from a first voltage at a first time point, and raises the pass voltage to a second voltage at a second time point. The second voltage is lower than a target voltage times a preset ratio The first time point is earlier than a start time point of a bit line voltage received by the selected memory cell, and the second time point occurs at the start time point of the bit line voltage.

Flash memory and operation method thereof for controlling raising speed of the read pass voltage

A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.

Memory device and write method thereof

A memory device and a program verification method thereof are provided. The write verification method includes: reading a previous page to obtain first read data, writing input data to a current page, reading the previous page or the current page to obtain second read data, and analyzing at least one of the first read data and the second read data to determine whether to back up at least one of the first read data and the input data to a redundant block of the memory device.

Memory device and program verification method thereof

Methods, systems and apparatus for effectively erasing blocks with few programmed pages are provided. In one aspect, a system includes a memory and a controller coupled to the memory. The memory includes blocks each having pages. The controller is configured to determine whether a threshold page with a particular page number in a block of the memory is programmed, to erase the block according to a normal erase action in response to determining that the threshold page is programmed, and to erase the block according to a particular erasing action that is configured to erase the block deeper than the normal erase action in response to determining that the threshold page is not programmed. The particular erasing action can include pre-programming the block before erasing the block, decreasing an erase verify voltage before erasing the block, or adding one or more erasing pulses with a new erasing voltage.

Erasing blocks with few programmed pages

Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.

Memory device and programming operation method thereof with different bit line voltages

A non-volatile memory and a program method thereof are provided. The program method of the non-volatile memory includes: setting a first incremental value, and providing a plurality of first pulses of incrementally increasing voltages in sequence according to the first incremental value for performing a programming operation on a plurality of non-volatile memory cells during a first time period; and setting a second incremental value, and providing a plurality of second pulses of incrementally increasing voltages in sequence according to the second incremental value for performing a programming operation on the non-volatile memory cells during a second time period which is after the first time period, wherein the first incremental value is smaller than the second incremental value.

Non-volatile memory and program method thereof

A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.

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Taichung, Taiwan

Ya-Jui Lee