Taiwan Semiconductor Manufacturing Comp. Ltd.

Ya Hui Chang

Ru-Gun Liu

Yu-Tien Shen

Yung-Sung Yen

Wei-Liang Lin

Ya-Wen Yeh

Chin-Hsiang Lin

Li-Te S Lin

Chien-Wen Lai

Shih-Chun Huang

Kuei-Shun Chen

Huicheng Chang

Keng-Chu Lin

Liang-Yin Chen

Chia-Cheng Chen

Joung-Wei Liou

Cheng-Han Wu

Chih-Ming Lai

Pinyen Lin

Ming-Feng Shieh

Burn Jeng Lin

Ken-Hsien Hsieh

Wei-Hao Wu

Hung-Chang Hsieh

Chia-Chu Liu

Tsong-Hua Ou

Po-Chin Chang

Chih-Min Hsiao

Chien Wen Lai

Chiu-Hsiang Chen

Ching-Yu Chang

Yee-Chia Yeo

Yen-Ming Chen

Jyu-Horng Shieh

Chih-Yuan Ting

Chi-Cheng Hung

Chun-Yen Chang

Chih-Kai Yang

Chien-Wei Wang

Yi-Nien Su

Chun-Hung Wu

Kuei-Liang Lu

Shu-Huei Suen

Hui OuYang

Yuan-Hsiang Lung

Wei-De Ho

Yu-Tse Lai

Chia-Fong Chang

Meng Jun Wang

Shih-Che Wang

Chung-Ming Wang

Minfeng Chen

Ching-Huang Chen

Yu Lun Liu

Ai-Jen Hung

Chi-Yuan Sun

Tsung-Lin Yang

Spencer Lin

Irene Ho

Shu-Hong Lin

Chih-Jung Chiang

Chang-Yi Tsai

Tsiao Chen Wu

A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Method of forming a semiconductor device

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

Pattern fidelity enhancement

A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

Photoresist and method of formation and use

A method of manufacturing a semiconductor device includes forming a first resist layer over a substrate, and forming a second resist layer over the first resist layer. The second resist layer is patterned to expose a portion of the first resist layer to form a second resist layer pattern. The first resist layer is exposed to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern. Portions of the first resist layer exposed to the XUV radiation diffracted by the second resist layer are removed.

Method of manufacturing a semiconductor device

In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Method of manufacturing semiconductor devices

A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Landing metal etch process for improved overlay control

A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Directional deposition for semiconductor fabrication

A structure includes a dielectric layer, and a metal line in the dielectric layer. The metal line has a first straight edge and a second straight edge extending in a lengthwise direction of the metal line. The first straight edge and the second straight edge are parallel to each other. A via is underlying and joined to the metal line. The via has a third straight edge underlying and vertically aligned to the first straight edge, and a first curved edge and a second curved edge connecting to opposite ends of the third straight edge.

Via-first self-aligned interconnect formation process

A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

Fine line patterning methods

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

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Hsinchu, Taiwan

Ya Hui Chang