Elite Semiconductor Memory Technology, Inc

Ya-Chun Lai

Jen-Shou Hsu

Po-Hsun Wu

A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.

Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit

A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells. The k redundant cells shares the precharge transistor and an inverted latch of the common stage circuit, and the fuse in the selected redundant cell affects the output of the corresponding fuse box. The comparator enabled by the comparator enable signal compares the fuse status address signal and a defective element address signal to generate a redundancy enable signal. The redundancy evaluation circuit has a small layout area.

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Hsinchu, Taiwan

Ya-Chun Lai