Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Ememory Technology Inc.

Au Optronics Corporation

Other

Macronix International Co., Ltd.

Via Technologies, Inc.

Copee Technology Company

Vishay General Semiconductor, Inc.

Twin Han Technology Co., Ltd.

Art Talent Industrial Limited

Ya-Chin King

Chrong-Jung Lin

Chrong Jung Lin

Yu-Der Chih

Jonathan Tsung-Yung Chang

Yun-Sheng Chen

Tzong-Sheng Chang

Ching-Hsiang Hsu

Burn Jeng Lin

Chih-Wei Chao

Chien-Sen Weng

Hsin-Yuan Yu

Wen Zhang Lin

Chao-I Wu

Shih-Jye Shen

Burn-Jeng Lin

Huang-Kui Chen

Yao-Hung Huang

Kung-Hong Lee

Jiun Shiung Wu

Woan-Yun Hsiao

Cheng-Hsiao Lai

Maybe Chen

Shi-Jiun Wang

Wang-Yi Lee

Hsin-Ming Chen

Tzu-Hsuan Hsu

Chia-Tien Peng

An-Thung Cho

Kuang-Yeu Hsieh

Feng-Yuan Gan

Kun-Chih Lin

Wei-Shuo Ho

Wen-Zhang Lin

May-Be Chen

Yi-Pei Tsai

Wen-Jen Chiang

An-Lun Lo

Cheng-Jun Lin

Li-Jui Chen

Chun-Lin Louis Chang

Kuang Yeu Hsieh

Meng-Yi Wu

Ming-Chou Ho

Shao-Hua Wang

Chieh Lee

Fu-Yuan Chen

Ching-Song Yang

Tzu Hsuan Hsu

Yu-Cheng Lin

Ming-Tai Chiang

Chih-Yang Chen

Hsin-Fen Chou

Sheng-Huei Dai

Hai-Ning Wang

Yueh-Ping Yu

Che-I Lin

Ming-Chiu Ho

Liang-Wei Lai

Chien-Ping Wang

Li-Yu Wang

Bo Yu Lin

A fabricating method of a resistive random access memory unit with one-way conduction characteristic includes performing an initializing step, a forming step and a reverse resetting step. The initializing step includes providing the resistive random access memory unit. The forming step includes applying a setting voltage on a lower metal layer, and coupling an upper metal layer to a ground voltage to transform the resistive random access memory unit to a low resistive state. The reverse resetting step includes coupling the lower metal layer to the ground voltage and applying a resetting voltage to the upper metal layer to transform the resistive random access memory unit to a one-way conduction state. A forward reading current is greater than a reverse reading current, and the forward reading current is less than 3000 times of the reverse reading current.

Resistive random access memory unit with one-way conduction characteristic and fabricating method thereof

Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Memory cell including programmable resistors with transistor components

A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

Resistive memory device with protrusion covered with resistance changing element and method for manufacturing the same

A semiconductor fabrication apparatus and a method of using the same are disclosed. In one aspect, the apparatus includes a holder configured to place a substrate and a radiation source configured to provide radiation to transfer a pattern onto the substrate. The apparatus also includes a plurality of sensing devices configured to provide a reference signal based on an intensity of the radiation when the substrate is not present. The apparatus further includes a controller, operatively coupled to the plurality of sensing devices, configured to adjust the intensity of the radiation based on the reference signal.

Semiconductor fabrication apparatus and method of using the same

A memory device includes a memory array comprising a plurality of one-time-programmable (OTP) memory cells. Each of the plurality of OTP memory cells comprises a select transistor, a diode, and a conductor fuse. The diode and the conductor fuse are coupled in series, with the select transistor coupled to a common node between the diode and the conductor fuse.

One-time-programmable memory devices

A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.

Memory device and system

A three-dimensional resistive random access memory structure includes a base layer, a first layer, a second layer, a third layer and a fourth layer. The first layer includes two first conductive layers and a first via. One of the two first conductive layers is electrically connected between the base layer and the first via. The second layer includes three second conductive layers and two second vias. Two first resistive elements are formed between one of the two second vias and two of the three second conductive layers. The third layer includes three third conductive layers and two third vias. Two second resistive elements are formed between one of the two third vias and two of the three third conductive layers. The fourth layer includes a fourth conductive layer. The fourth conductive layer is electrically connected to the two third vias.

Three-dimensional resistive random access memory structure

A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.

Semiconductor device, manufacturing method thereof, and detecting method using the same

A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Semiconductor detector

A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an energy sensing film. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The energy sensing film is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the energy sensing film is contacted with an external energy source, and the induced charge is stored in the floating gate.

Defect measurement method

A low voltage one-time-programmable memory includes a first conductive layer, a first via, a second conductive layer, a select transistor, a second via and a third conductive layer. The first via is electrically connected to the first conductive layer. The second conductive layer is electrically connected to the first via. The select transistor is electrically connected to the second conductive layer. The second via is electrically connected to the second conductive layer. The third conductive layer is electrically connected to the second via. A first current passed through the second via is a sum of a second current passed through the first via and a third current passed through the select transistor.

Low voltage one-time-programmable memory and array thereof

Resistive memory device and method for manufacturing with protrusion of electrode

A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

Detection using semiconductor detector

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

Semiconductor device and method of manufacturing the same

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Taipei, Taiwan

Ya-Chin King