Taiwan Semiconductor Manufacturing Comp. Ltd.

Ya-Chi Chou

Ting-Wei Chiang

Hui-Zhong Zhuang

Ru-Gun Liu

Chih-Ming Lai

Shih-Ming Chang

Jung-Chan Yang

Yu-Xuan Huang

Yi-Hsiung Lin

Guo-Huei Wu

Yu-Jung Chang

Pochun Wang

Li-Chun Tien

Po-Hsiang Huang

Chi-Yu Lu

Pin-Dai Sue

Fong-Yuan Chang

Chun-Fu Chen

Shun-Li Chen

Hsiang Jen Tseng

Chi-Yeh Yu

Wei-Yi Hu

You-Cheng Xiao

Shih-Hsuan Chien

A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

Integrated circuit having fins crossing cell boundary

An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Integrated circuit and method of manufacturing same

A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

Dummy cells placed adjacent functional blocks

An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Buried metal track and methods forming same

An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin.

Method and system for pin layout

A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern.

Semiconductor device having engineering change order (ECO) cells and method of using

A method performed by at least one processor includes selecting a pin in a cell, determining a type of the pin, assigning a first pin access and a second pin access of the pin to a same patterning group at different patterning tracks when the pin is determined to be a cross-track pin, determining whether a pin access of a first pin and a pin access of a second pin disposed adjacent to the first pin in the cell are on a same patterning track, separating the first pin and the second pin from each other by a first predetermined distance when the pin accesses are determined to not be on a same patterning track, and separating the first pin and the second pin from each other by a second predetermined distance when the pin accesses are determined to be on a same patterning track.

A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

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Hsinchu, Taiwan

Ya-Chi Chou