Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Ya-Chen Kao

Harry-Hak-Lay Chuang

Chun-Jung Lin

Wei Cheng Wu

Wei-Cheng Wu

Tien-Wei Chiang

Yu-Jen Wang

Hung-Cheng Sung

Chen-Ming Huang

Yi Hsien Lu

Ming-Te Liu

Shih-Chang Liu

Chin-Yi Huang

Wen-Cheng Chen

Meng-Han Lin

Wen-Ting Chu

Chung-Yi Yu

Harry Hak-Lay Chuang

Chen-Chin Liu

Chih-Ren Hsieh

Chih-Pin Huang

Fang-Lan Chu

Chang-Jen Hsieh

Chia-Shiung Tsai

Fu-Lung Hsueh

Chung-Cheng Chou

Sheng-Huang Huang

Jun-De Jin

Chi-Hsin Lo

Tong-Chern Ong

Chih-Huang Lai

Kuo-Feng Huang

Sa-Lly Liu

Ping-Lin Yang

Der-Shin Shyu

Han-Ping Chen

Li-Wen Chang

Cheng-Yuan Tsai

Chih-Ming Chen

Hung-Chang Yu

Feng-Jia Shiu

Chwen Yu

Li-Feng Teng

Kai-Chun Lin

Wang-Shuo Kao

Hsu-Chen Cheng

Shang-Chiang Lin

Yu-Han Chiang

Kai-Chieh Chang

Yung-Tao Lin

Tsai-Fen Wu

Jui-Sheng Wu

Young-Shying Chen

The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.

High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory

A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.

Integrated circuit structure and manufacturing method thereof

Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Cell-like floating-gate test structure

A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.

Method for manufacturing semiconductor device including dummy gate electrodes

A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.

Memory device with metal gate

Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.

Integration of magneto-resistive random access memory and capacitor

The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-&#x3ba; metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

A display device of the present invention includes a light source apparatus and a rear light transmitting module disposed opposite a first light emitting surface of the light source apparatus. The rear light transmitting module includes a first transmitting layer and a second transmitting layer. The first transmitting layer has a plurality of first prisms arranged side by side and respectively protruding toward the first light emitting surface. The second transmitting layer is overlapped with the first transmitting layer on one side thereof opposite the first light emitting surface, and has a plurality of second prisms arranged side by side and respectively protruding toward the first transmitting layer. A vertical projection range of the first prisms on the first light emitting surface is misaligned with a vertical projection range of the second prisms on the first light emitting surface.

Display device with rear light transmitting module

A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.

Method for manufacturing semiconductor device with metal gate memory device and metal gate logic device

The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.

The present invention provides a display device including a display panel and a haze layer. The display panel includes a plurality of pixels and a color determining surface. The orthogonal projection of each of the plurality of pixels onto the color determining surface forms a plurality of adjacent pixel ranges. The haze layer is disposed on a side of the color determining surface and has a haze surface facing away from the color determining surface. The haze layer has a scattering coefficient ranging from &#x2212;1.4 to 0. The haze surface includes a first location corresponding to the center of the first pixel range, and a second location corresponding to a location away from the first edge towards the second pixel range wherein the distance therebetween ranges from 87 &#x3bc;m to 174 &#x3bc;m.

Display device with haze layer

HKMG high voltage CMOS for embedded non-volatile memory

Growing community of inventors

Fuxing, China

Ya-Chen Kao