Intel Corporation

Xuye Li

David D Donofrio

An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exponents. A FP multiply-add (MAD) unit performs a multiply-and-add operation on the intermediate argument, a second argument, and a third argument to produce a result having a result mantissa and a result exponent. The second and third arguments have second and third mantissas and exponents, respectively.

Enhanced floating-point unit for extended functions

In one embodiment a visual representation of a pulse shape is created. points of the visual representation of the pulse shape are moved to correspond to a representation of an ideal pulse. Pulse shape coefficient registers are updated to represent the visual representation of the pulse shape such that the pulse shape is adjusted to correspond to the pulse template.

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Folsom, CA, United States of America

Xuye Li