Advanced Micro Devices Corporation

Xuwei Chen

Dazheng Wang

A uniform cache for fast data access including a plurality of compute units (CUs) and a plurality of LO caches with an arrangement in a network configuration where each one of CUs is surrounded by a first group of the plurality of LO caches and each of the plurality of LO caches is surrounded by a LO cache group and CU group. One of CUs, upon a request for data, queries the surrounding first group of LO caches to satisfy the request. If the first group of LO caches fails to satisfy the data request, the first group of the plurality of LO caches queries a second group of adjacent LO caches to satisfy the request. If the second group of adjacent LO caches fails to satisfy the data request, the second group of adjacent LO caches propagating the query to the next group of LO caches.

Uniform cache system for fast data access

A uniform cache for fast data access including a plurality of compute units (CUs) and a plurality of L0 caches with an arrangement in a network configuration where each one of CUs is surrounded by a first group of the plurality of L0 caches and each of the plurality of L0 caches is surrounded by a L0 cache group and CU group. One of CUs, upon a request for data, queries the surrounding first group of L0 caches to satisfy the request. If the first group of L0 caches fails to satisfy the data request, the first group of the plurality of L0 caches queries a second group of adjacent LO caches to satisfy the request. If the second group of adjacent L0 caches fails to satisfy the data request, the second group of adjacent L0 caches propagating the query to the next group of L0 caches.

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Shanghai, China

Xuwei Chen