Huawei Technologies Co., Limited

Future Wei Technologies, Inc.

Xusheng Liu

Gang Zhao

Yongyao Li

Howard S David

Zewen Wang

Wenliang Li

Zhong Yan

Yongwei Chen

Ertang Xie

Wang Xiong

Zhenhua Yuan

A printed circuit board includes a plurality of layer structures disposed in a stacked manner, and the printed circuit board has a disposing face. A differential pair unit and a shielding structure for shielding the differential pair unit are disposed on the disposing face. The differential pair unit includes two signal via holes, each signal via hole passes through the plurality of layer structures, and an anti-pad corresponding to each signal via hole is disposed on a ground layer through which the signal via hole passes. A part of metal of a ground layer is spaced between two anti-pads. Each signal corresponds to one anti-pad, and a ground layer is spaced between anti-pads.

Printed circuit board, backplane architecture system, and communication device

A printed circuit board includes a connector insertion area including many rows of crimping holes, each row of crimping holes includes at least two pairs of signal crimping holes (SCHs), and each pair of SCHs includes two SCHs. In a row arrangement direction of the crimping holes, at least one ground crimping hole (GCH) is arranged on either side of each pair of SCHs. A depth of the GCH is greater than or equal to a depth of the SCH, the GCH includes a main hole and a shielding component on at least one side of the main hole, a part of a side wall of the main hole is a part of a side wall of the shielding component, and a sum of lengths of the main hole and the shielding component in a first direction is greater than a length of the SCHs in the first direction.

Printed circuit board, communications device, and manufacturing method

A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controller

A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

Receiver equalization and stressed eye testing system

Growing community of inventors

Shenzhen, China

Xusheng Liu