Synopsys, Inc.

Xun Liu

Gary K Yeap

Jitendra Kumar Gupta

Ksenia Roze

Paul Chang

Shamik Saha

Lan Luo

Jennifer Song Yon Pyon

A description of an interconnect channel within an interposer (such as a Universal Chiplet Interconnect Express™ (UCIe) channel) includes first bump locations for a first interface to the interconnect channel on a first die, second bump locations for a second interface to the interconnect channel on a second die, and nets connecting corresponding first and second bump locations for the two interfaces on the two dies. A processing device partitions the interconnect channel into subchannels. The subchannels include corresponding clusters of first and second bump locations connected by nets. The bounding boxes for the subchannels are non-overlapping. For each subchannel, the nets within the subchannel are routed.

Interposer routing for universal chiplet interconnect express™ channels by partitioning into subchannels

A processing device generates a routing graph in accordance with a three-dimensional integrated circuit (3DIC) configuration of a 3DIC device. The processing device performs net routing with respect to the routing graph. The processing device determines, based on a net routing result of the net routing, whether at least one valid modified routing graph exists in view of an initial netlist corresponding to the 3DIC device. In response to determining that at least one valid modified routing graph exists, the processing device selects a modified routing graph from the at least one valid modified routing graph. The processing device generates, based on the modified routing graph, an updated netlist that satisfies the 3DIC configuration and is logically equivalent to the initial netlist.

Generating and utilizing manufacturable netlists of three-dimensional integrated circuits

A method includes partitioning, within an interposer IC design on which are disposed a first die and a second die, a first bump array into first cluster regions of bumps and a second bump array into second cluster regions of bumps. Creating multiple sub-channels between respective bump cluster regions. Identifying a set of trunk areas positioned between the first bump array and the second bump array, each trunk area to include net lines, each sub-channel to include at least one trunk area of the set of trunk areas. Identifying connector regions to route the net lines between adjacent trunk areas of the set of trunk areas. Assigning, based on layers available for routing, a routing layer to each net line that is to be routed in each respective sub-channel. The method includes routing, based on the assigning, the net lines through the set of trunk areas and the connector regions.

Routing of high-speed, high-throughput interconnects in integrated circuits

Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method includes identifying candidate nets within a netlist. A bounding box that includes one or more nets of the candidate nets is determined. Once the bounding box is determined, the orientation of the box is determined and used to determine a pattern of bumps within the bounding box. Finally, a subchannel is generated based on the pattern of bumps.

Automatic channel identification of high-bandwidth memory channels for auto-routing

A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern () including a physical layout of connectors () and pad pins () is associated with a mapping of connections between the connectors () and the pad pins (). A processor () identifies instances () of the pattern () within a design image () of an integrated circuit (IC) die using a machine learning model. The design image () includes a physical layout of connectors () and pad pins (). For each identified instance () of the pattern () within the design image (), the mapping of connections is assigned to respective connectors () and pad pins () in the identified instance ().

Pattern based die connector assignment using machine learning image recognition

Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be 'clones,' where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

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Durham, NC, United States of America

Xun Liu