Seagate Technology Incorporated

Spansion Llc.

Xuguang Alan Wang

Hongyue Liu

Yi He

Dimitar Velikov Dimitrov

Yiran Chen

Hai Li

Zhizheng Liu

Darlene G Hamilton

Ming Sang Kwan

Sung-Yong Chung

Xiaobin Wang

Nancy S Leong

Guowei Wang

Sung-Chul Lee

Yugi Mizuguchi

Song Sheng Xue

Michael Xuefei Tang

Ming-Sang Kwan

Shuiyuan Huang

Yong Lu

Timothy J Thurgate

Edward Franklin Runnion

Sheung-Hee Park

Wing Leung

Mark W Randolph

Ashot Melik-Martirosian

Gulzar Ahmed Kathawala

Gwyn Robert Jones

Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.

Non-volatile multi-bit memory with programmable capacitance

A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Controlling AC disturbance while programming

A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.

Diode assisted switching spin-transfer torque memory unit

A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.

Three dimensionally stacked non volatile memory units

A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.

Shared bit line and source line resistive sense memory structure

A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.

Static source plane in STRAM

Static source plane in stram

Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.

Non-volatile memory with programmable capacitance

A memory array includes a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.

Growing community of inventors

Eden Prairie, MN, United States of America

Xuguang Alan Wang