Xilinx, Inc.

Freescale Semiconductor,inc.

Xuewen Jiang

Zhaoyin D Wu

Parag Upadhyaya

Adebabay M Bekele

Shuxian Wu

Jing Jing

Aman Sewani

Parag Upadhyahya

An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.

Interdigitated capacitor having digits of varying width

One embodiment of an integrated circuit includes a local circuit block, a first power supply for supplying power to a first terminal of the local circuit block, a second power supply for supplying power to a second terminal of the local circuit block, a first transmission gate coupled between the second terminal of the local circuit block and a current path from the second power supply, and a second transmission gate coupled between the current path from the second power supply and a gate of a p-type metal-oxide-semiconductor (PMOS) transistor in the first transmission gate, the second transmission gate including a single transistor.

Method and apparatus for powering down a dual supply current source

An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.

Symmetrical center tap inductor structure

An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include an isolation wall formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger.

Integrated circuit inductor having a patterned ground shield

A method and apparatus for dividing clock frequencies are disclosed. For example, a circuit according to one embodiment of includes a high-speed divider and a plurality of programmable dividers cascading with the high-speed divider, wherein the plurality of programmable dividers are of a lower speed than the high-speed divider.

Method and apparatus for dividing clock frequencies

A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the second varactor are coupled to a first input node. A first gate node for the first varactor is coupled to a first output node. A second gate node for the second varactor is coupled to a second output node. A third gate node for the third varactor and a fourth gate node for the fourth varactor are coupled to a second input node. A third source-drain node of the third varactor is coupled to the first output node. A fourth source-drain node of the fourth varactor is coupled to the second output node. In other embodiments, varactor circuits block and re-center VCO output CML.

Varactor circuit and voltage-controlled oscillation

A double-balanced sinusoidal mixing phase interpolator circuit comprises: a double-balanced gain stage having a first input for receiving a first phasor clock, a second input for receiving a second phasor clock, and a phase interpolator (PI) output, wherein the double-balance gain stage includes (i) a first gain stage having a positive input side and a negative input side for the first phasor clock and (ii) a second gain stage having a positive input side and a negative input side for the second phasor clock; and a sinusoidal digital-to-analog (DAC) stage coupled to the double-balanced gain stage and configured to implement sinusoidal weighting of positive and negative sides of differential DAC current for the first phasor clock and positive and negative sides of differential DAC current for the second phasor clock, wherein the sinusoidal weighting provides uniformly spaced phase steps in the phase interpolator (PI) output.

Double-balanced sinusoidal mixing phase interpolator circuit and method

A square wave to pseudo-sinusoidal clock conversion circuit comprises first and second stages. The first stage includes a cross-coupled differential pairs input gain stage having positive and negative input sides. Responsive to a differential square wave clock input, the first stage provides a first pass balanced differential clock with pull-up and pull-down symmetry. The second stage comprises positive and negative output side push-pull with low pass filter circuits, wherein the positive and negative output side push-pull with low pass filter circuits are responsive to the first pass balanced differential clock from the first stage for producing an output pseudo-sinusoidal clock that comprises a nearly sinusoidal output with slew rate controlled and clock waveform pull-up and pull-down symmetry for each of a respective one of the positive and negative output sides.

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Chandler, AZ, United States of America

Xuewen Jiang