Huawei International Pte. Ltd.

Agency for Science, Technology and Research

Xuesong Chen

Rui Yu

Theng Tee Yeo

Chao Yuan

Lee Guek Doreen Yeo

Zhan Yu

Rajinder Singh

Wooi Gan Yeoh

Pradeep Basappa Khannur

Harya Wicaksana

Changqing Xu

Liu Supeng

Supeng Liu

A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.

Time-to-digital converter

A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.

Digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit

The embodiments of the invention provide a method and device for radio frequency (RF) limiting. The device for RF limiting comprises: an analog limiter configured to limit a voltage of a RF input to a predetermined safe range during power-off or power-up until a disable control signal is received from the digital controller, a sensing circuit configured to sense a plurality of shunting currents provided by the analog limiter in sequence to determine a value of each bit of a preset current sensing code and sense the limiting voltage, a digital controller configured to control the digital limiter to perform RF limiting function based on the value of each bit of the preset current sensing code, and control the analog limiter to stop limiting the voltage of the RF input if the limiting voltage is within a predetermined acceptable voltage range.

Method and device for radio frequency voltage limiting

A near field communication (NFC) device configured to use in preparing a carrier signal for active load modulation supporting both synchronous and asynchronous transmissions. The NFC device comprises a local clock generator for generating a reference clock signal (REF_CLK), a clock extractor for recovering a clock signal (EXT_CLK) generated by an NFC initiator device, a frequency tracking module (FTM) for performing a frequency tracking operation based on an input clock signal (REF_CLK or EXT_CLK) to produce a FTM output with its frequency aligned with the input clock signal, and a phase tracking module (PTM) for performing a phase tracking operation on the FTM output based on EXT_CLK to produce a PTM output with its phase aligned with EXT_CLK.

Active load modulation technique in near field communication

Embodiments of the invention provide a system and method for direct RF sampling a Near Field Communication (NFC) receiver at a rate higher than the carrier frequency by reducing and shifting requirements at a front end analog module to a digital module.

Apparatus and method for direct radio frequency (RF) sampling in near field communication (NFC) devices

A radio frequency identification transceiver is disclosed. The radio frequency identification transceiver includes: a transmitter path, including; a pulse shaper to tunably shape the pulse of a signal to be transmitted in different predefined frequency ranges; a modulator to modulate the shaped pulse to be transmitted into one of a plurality of predefined frequency ranges; a receiver path, including: a demodulator to demodulate a received signal from a plurality of predefined frequency ranges.

Growing community of inventors

Singapore, Singapore

Xuesong Chen