Marvell International Limited

Marvellworld Trade Ltd.

Seagate Technology Incorporated

Shannon Systems Ltd.

Carnegie Mellon University

Marvell Intentional Ltd.

Xueshi Yang

Zining Wu

Gregory Burd

Shashi Kiran Chilappagari

Nedeljko Varnica

Pantas Sutardja

Qiyue Zou

Michael Madden

Erozan Mehmet Kurtas

Shaohua Yang

Hongwei Song

Zhen Zhou

Aditya Ramamoorthy

Zhengang Chen

Panu Chaichanavong

Mehmet Faith Erden

Yu-Yao Chang

Shumei Song

Heng Tang

Lau Nguyen

Hongxin Song

Sui-Hung Fred Au

Tony Yoon

Seo-How Low

Chi Kong Lee

Mark David Bedillion

ChengKuo Huang

Alexander Kuznetsov

Liang-Chieh Chen

Chen Kuo Huang

Fei Sun

Joachim Walter Ahner

Ke Han

Robert Earl Rottmayer

Siu-Hung Fred Au

Man Cheung

Andreas Karl Roelofs

Mark Ian Lutwyche

David Bruce Anderson

Martin Gerard Forrester

Earl Chrzaszcz Johns

Ningzhong Miao

Sami Iren

Sean Lee

Darren William Karns

Edward Stephen Skalko

Sashi Kiran Chilappagari

Heng Teng

Andre Y L Liem

Rohit Negi

Xun Zhang

Grace Pao Yi Chen

Space allocation for non-volatile memory is shown. A controller establish a first namespace set by allocating the non-volatile memory in units of a first storage unit, and establishes a second namespace set by allocating the non-volatile memory in units of a second storage unit. The first storage unit is bigger than or equal to the second storage unit, and the first storage unit has better input and output isolation than the second storage unit. The first namespace set and the second namespace set are in the different tiers in a hierarchical storage architecture.

Data storage device, and non-volatile memory control method

A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks for storing data and each block includes a plurality of pages. The controller is configured to convert a host read command into a read-operation instruction to the flash memory to perform a default read operation to read page data from the flash memory. The default read operation has a default read threshold voltage. In response to a failure of the default read operation, the controller is configured to sequentially perform a read operation on the flash memory using a read threshold voltage with respect to each entry of a plurality of entries in a read-retry table, and replace the default read threshold voltage with the read threshold voltage corresponding to the read operation being successfully performed.

Data storage device and adaptive data-reading method thereof

A data storage device with high security is disclosed. A nonvolatile memory provides a storage space divided into a plurality of first-level cells. The first-level cells are grouped into a plurality of second-level cells with each second-level cell containing several first-level cells. Each of the plurality of first-level cells is provided with checking and correcting code by a control unit. When reading a specified first-level cell, the control unit checks data in the specified first-level cell based on the checking and correcting code of the specified first-level cell and thereby performs a self-test on another space of a specified second-level cell. The specified first-level cell is provided in the specified second-level cell.

Data storage device and method for data error management

A method and system provide for storage device metadata management. The storage device metadata management method comprises: a superblock is formed of at least one erase block; the superblock reserves a space for storing metadata related to the superblock; the metadata related to the superblock comprises a serial number distributed to the superblock and address mapping information in the superblock; the address mapping information stores a mapping relationship of a physical block address to a logic block address (S); when data is written into the superblock, the address mapping information corresponding to the data is also written into the superblock (S); when a system is recovered, a page table of the storage system is recovered according to the address mapping information of the superblock; the page table marks a mapping relationship of a logic block address to a physical block address (S). The above technical solution can ensure a complete recovery of the page table during startup, as well as ensure a normal operation of the storage device when started.

Method and system for storage device metadata management and processing

A RAID system and method based on a solid-state storage medium. The system includes a plurality of solid-state storage devices and a main control unit. Each solid-state storage device includes a solid-state storage medium and a controller for controlling reading and writing of the solid-state storage medium. The main control unit is electrically connected to the controller of each of the solid-state storage devices in a RAID array. The main control unit is used for performing address mapping from a logical block address in the RAID array to a physical block address of the flash memory solid-state storage device. The address mapping and the RAID function can be integrated to solve the problems of write amplification and low performance. The unified management of address mapping of the solid-state storage devices can be implemented to improve the efficiency of garbage collection and wear leveling of the solid-state storage system.

Raid system and method based on solid-state storage medium

A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.

Host device, access system, and access method

A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.

Methods for reconfiguring a storage controller when control logic fails and apparatuses using the same

Provided are a power failure protection method and solid state drive (SSD). The SSD comprises: a power-failure detection device, for monitoring in real time whether the power supply is abnormal; a power-failure protection device performs a power-failure protection operation when the power supply is monitored to be abnormal: breaking a connection with a host system bus, an SSD internal clock breaking from a system bus clock and writing data in the SSD cache into a storage unit of the SSD by using the SSD internal clock. The technical solution ensures completion of the data protection operations by utilizing a remaining capacity, thus ensuring data integrity.

Power-failure protection method and solid state drive

An auto-adaptive system to implement partial write buffering for storage systems comprises: dynamically determining a wiring method for a data queue which needs to be written, and on the basis of a determination result, directly writing to a storage medium data suited to being written directly, and as for data suited for being written after being cached, caching the data by a caching device and then writing the data to the storage medium. A dynamic caching system uses the above method. The method and system significantly reduce the space requirements for caching, enable fault tolerance integration, and improve system performance.

Auto-adaptive system to implement partial write buffering for storage systems dynamic caching method and system for data storage system

A storage system for constructing RAID on the basis of flash memory comprises: one or more RAID processors and a plurality of flash memories. The RAID processor comprises a plurality of read-and-write processing units, a data block pointer unit, a data block counter and a parity check code buffer. One read and write processing unit can control one or more flash memory units. A method for constructing RAID in a storage system on the basis of flash memory can realize the function of RAID in a very small logic area and approximately negligible time and realize the unification of the function and performance of a storage system such as an enterprise-level SSD.

Method for calculating raids parity code on interleaving and out of order data streams, and a system using the same

A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page.

System and method for writing pilot data interspersed with user data for estimating disturbance experienced by user data

Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.

Selectively scheduling memory accesses in parallel based on access speeds of memory

Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.

Selectively programming data in multi-level cell memory

A system including a read module, a delay buffer, and a least mean square module. The read module is configured to read charge levels of memory cells of a nonvolatile memory and to generate read signals based on the charge levels of the memory cells of the nonvolatile memory. The delay buffer is configured to delay the read signals and to generate delayed read signals. The least mean square module is configured to generate mean values of the charge levels used to program the memory cells based on (i) differences between the read signals and the delayed read signals and (ii) a scaling factor. The scaling factor is based on variations in the charge levels due to cycling of the memory cells of the nonvolatile memory.

Programming nonvolatile memory based on statistical analysis of charge level distributions of memory cells

A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values. The one or more of the interference values are selected based on (i) the state to which the memory cell is to be programmed, and (ii) the states of the one or more memory cells.

Write pre-compensation for nonvolatile memory

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Cupertino, CA, United States of America

Xueshi Yang