Lattice Semiconductor Corporation

Xueping Jiang

Ming Qu

Ji Zhao

Kochung Lee

Xiang Zhu

Method and system for generating a multiple width (e.g., 16-bit width) pseudo-random number (PRN). Each of first and second 8-bit width PRNs is generated, using first and second LFSR configurations that incorporate first and second characteristic polynomials, at least one of which is irreducible. The first and second 8-bit PRNs are generated on a rising edge and on a falling edge, respectively, of a clock signal. The first and second 8-bit PRNs are combined by concatenation or by interleaving to form a 16-bit, or other multiple width, PRN.

Multiple width random number generation

High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number ( ) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number ( ) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.

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Cupertino, CA, United States of America

Xueping Jiang