Globalfoundries Inc.

Globalfoundries U.S. Inc.

Xuemei Hui

Wei Zhao

Shafiullah Syed

Don Raymond Blackwell

Qiao Yang

A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

Static random access memory (SRAM) cell with variable toggle threshold voltage and memory circuit including SRAM cells

Embodiments of the present disclosure provide a circuit structure including four FDSOI transistors coupled to a single output node at their respective back-gate terminals. An input voltage line may be coupled to the gate terminal of two transistors. The two transistors each may be coupled to the gate terminal of two other transistors at one of their source or drain terminals via a junction node. The other two transistors may be coupled to the single output node through one of their source or drain terminals. The other source or drain terminal of each transistor may be electrically coupled to a source voltage line or a drain voltage line.

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Shanghai, China

Xuemei Hui