Boe Technology Group Co., Ltd.

Hefei Boe Joint Technology Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Boe Technology Groupco., Ltd.

Boe Technology Group Go., Ltd.

Xuehuan Feng

Yongqian Li

Can Yuan

Zhidong Yuan

Meng Li

Pan Xu

Zhenfei Cai

Xing Zhang

Dacheng Zhang

Zhongyuan Wu

Sixiang Wu

Hao Liu

Lang Liu

Qi Hu

Xuelian Cheng

Zehua Ding

Guoying Wang

Xing Yao

Song Meng

Yicheng Lin

Quanhu Li

Ying Han

Zhan Gao

Mingi Chu

Yubao Kong

Wei Li

Lin Sun

Ming Wang

Wei Chen

Chen Hui Xu

Zheng Liu

Min He

Fei Fei Li

Jingquan Wang

Jingbo Xu

Wenchao Bao

Huihui Li

Xiaolong Wei

Dongxu Han

Mengyu Luan

Haixia Xu

Youyuan Hu

Xinzhu Wang

Xinfeng Wu

Jianye Zhang

Bo Mao

Liu Wu

Chen Xu

Chao Jiao

Taejin Kim

Mingming Xie

Provided are a display panel, a driving method therefor and a display device. The display panel includes pixel driving circuits and a first gate driving circuit. The pixel driving circuit includes a driving circuit connected to first to third nodes for inputting a driving current to the third node through the second node, and a first switching unit having a first terminal connected to the third node and a second terminal connected to a sensing signal terminal for electrically connecting, in response to a signal at a control terminal thereof, the third node and sensing signal terminal. The first gate driving circuit includes a first output terminal corresponding to the pixel driving circuit and connected to the control terminal. The first output terminal outputs an active level pulse during data writing stage and black frame insertion stage of a driving cycle of the pixel driving circuit corresponding thereto.

Display panel, driving method therefor, and display device

An array substrate and a display device are provided. The array substrate includes a base substrate, and gate lines, a gate driving structure, an interconnecting structure and an insulating layer. The gate lines are electrically connected with the gate driving structure through the interconnecting structure; the insulating layer is located between the gate lines and the interconnecting structure, and includes a first via hole and a second via hole. The gate line includes a first connecting portion and a second connecting portion, and the second connecting portion is located between the gate driving structure and the first connecting portion; the first connecting portion is electrically connected with the interconnecting structure through the first via hole, and a straight line extending in a direction perpendicular to the base substrate passes through the second connecting portion, the second via hole and the interconnecting structure in turn.

Array substrate and display device

A shift register is provided and includes a display input reset circuit, an inverter circuit, at least one output circuit and a first detection circuit; the display input reset circuit, the inverter circuit and the output circuit are connected to a pull-up node; the inverter circuit and the at least one output circuit are connected to a pull-down node; the first detection circuit is connected to a signal acquisition point, an acquisition control terminal, and a first signal detection line, and configured to acquire a voltage at the signal acquisition point in response to a signal from the acquisition control terminal and output a detection voltage corresponding to the acquired voltage to the first signal detection line, an external first chip adjusts an active level voltage from the third power supply terminal according to the detection voltage; the signal acquisition point includes the pull-down node and/or a signal output terminal.

Shift register, gate driving circuit, and display apparatus

A method for compensating display brightness, a circuit for compensating display brightness, and a display device are provided. The method for compensating display brightness is applicable to a display device. A first group of sub-pixel rows in the display device perform normal display and black frame insertion display in a same frame display period. A second group of sub-pixel rows in the display device perform normal display in a current frame display period and an adjacent next frame display period, and perform black insertion display in the adjacent next frame display period. A first interval period is provided between the current frame display period and the adjacent next frame display period. The method for compensating includes: compensating luminous brightness of the first group of sub-pixel rows and/or compensating luminous brightness of the second group of sub-pixel rows.

Method for compensating display brightness, circuit for compensating display brightness, and display device

A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.

Shift register unit, driving method, gate driving circuit, and display device

The present disclosure provides a shift register unit, including: a first sensing control input circuit and at least one first output circuit; the shift register unit further includes: a first voltage control circuit, a first sensing input leakage prevention circuit and a first current limiting circuit; the first sensing control input circuit is connected to a first pull-up node through the first sensing input leakage prevention circuit, the first sensing control input circuit is connected to the first sensing input leakage prevention circuit at a first sensing input leakage prevention node connected to a first voltage control node, the first sensing input leakage prevention circuit is connected to the clock control signal input terminal and is configured to control on/off between the first sensing input leakage prevention node and the first pull-up node; the first current limiting circuit is connected to the first voltage control node.

Shift register unit, gate driving circuit and display substrate

A shift register unit, a driving method thereof, and a gate driving circuit are disclosed. The shift register unit includes: an input circuit configured to receive an input signal from an input signal terminal and output the input signal to a voltage stabilizer node; a voltage-stabilizing circuit configured to input potential of the voltage stabilizer node to a pull-up node and control potential of the voltage stabilizer node; an output circuit configured to receive a clock signal from a clock signal terminal and provide an output signal to an output signal terminal based on the clock signal received under control of the potential of the pull-up node; and a control circuit configured to control potential of the output signal terminal under control of the potential of the pull-up node.

Shift register unit, driving method thereof, and gate driving circuit

A pixel circuit includes: a driving sub-circuit, a sensing sub-circuit, a light-emitting control sub-circuit, a sensing control sub-circuit, a light-emitting device and a sensing terminal. The driving sub-circuit includes a first terminal and a second terminal coupled to the light-emitting device, and is configured to write a data signal into the driving sub-circuit in response to a first scan signal and control an electrical signal flowing through the driving sub-circuit according to the data signal. The sensing sub-circuit is configured to connect the second terminal to the sensing terminal in response to a second scan signal. The light-emitting control sub-circuit is configured to connect a first voltage terminal to the first terminal in response to a light-emitting control signal. The sensing control sub-circuit is configured to connect a second voltage terminal to the first terminal in response to a sensing control signal provided by a sensing control terminal.

Pixel circuit, driving method of pixel circuit and display apparatus

Embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. The shift register includes a light emitting drive output module configured to supply a first voltage of a first power supply terminal to a light emitting control drive signal output terminal in response to control of a voltage at a third node, to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of a voltage at a second node, and to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of the second voltage at the second power supply terminal.

Shift register, gate drive circuit and display device

The present disclosure relates to the field of display technology, and describes a pixel driving circuit detection method, a display panel, a driving method thereof, and a display device. The detection method includes inputting a reference voltage to the data line during at least part of the initial phase; turning on the first and second switch sub-circuits during the charging phase, to input the detection voltage to the data line, while inputting the reset voltage to the sensing line; turning on the second switch sub-circuit during the charging phase, to input the driving current by the driving transistor to the sensing line under the effect of the detection voltage; turning off the first and second switch sub-circuits during the detection phase, to detect the voltage on the sensing line; and obtaining the mobility of the driving transistor according to the voltage on the sensing line detected in the detection phase.

Pixel circuit detection method, display panel driving method, and display device

A shift register circuit includes an input sub-circuit, an output sub-circuit, a control sub-circuit and a compensation sub-circuit. The input sub-circuit is configured to, under control of a first input signal received at a first input signal terminal, transmit the first input signal to a pull-up node. The output sub-circuit is configured to transmit a first clock signal received at a first clock signal terminal to a first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal received at a first control signal terminal. The compensation sub-circuit is configured to transmit a voltage at a seventh node to the pull-up node under control of a seventh clock signal received at a seventh clock signal terminal.

Shift register circuit, gate driver circuit and driving method therefor, and display apparatus

The present disclosure provides a display device, a gate drive circuit, a shift register unit and a driving method thereof. The shift register unit includes an input subcircuit configured to control a voltage at the first node under voltage control of the input control end; a signal output subcircuit configured to control disconnection and conduction between the clock signal ends and respective signal output ends under voltage control of the first node; a first control subcircuit configured to control the voltage at the first node under voltage control of the first control signal end.

Display device, gate drive circuit, shift register unit and driving method thereof

The present disclosure provides shift register unit, including: sensing control circuit connected to sensing signal input terminal, random signal input terminal, and sensing control node, and configured to write signal provided by sensing signal input terminal to sensing control node in response to active level signal provided by random signal input terminal; first sensing input circuit connected to clock control signal input terminal, sensing control node, and first pull-up node, and configured to write signal provided by clock control signal input terminal to first pull-up node only in response to active level signal at sensing control node; and first driving output circuit connected to first pull-up node, first driving clock signal input terminal, and first driving signal output terminal, and configured to write signal provided by first driving clock signal input terminal to first driving signal output terminal in response to active level signal at first pull-up node.

Shift register unit, gate driving circuit, and gate driving method

A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein the first sub-circuit includes a first input circuit and a first output circuit; the second sub-circuit includes a second input circuit and a second output circuit; the leakage prevention circuit is configured to control a level of a leakage prevention node under control of the level of the first node, so as to turn off a circuit connected between the first node and the leakage prevention node; and the blanking input sub-circuit is connected to the first node and the second node, and is configured to receive a selection control signal and a first clock signal, and control the level of the first node and the level of the second node.

Shift register unit, gate driving circuit, display device and driving method

Disclosed is a display panel including a base substrate (), and a gate drive circuit (), a plurality of clock signal lines, and a plurality of connecting lines () that are disposed on the base substrate (). The plurality of clock signal lines are located on a side of the gate drive circuit () along a first direction (X) and are arranged in sequence. Each connecting line () is electrically connected with the gate drive circuit () and a clock signal line. At least one connecting line () includes a load adjusting portion () configured to compensate for a load difference between different clock signal lines. An orthographic projection of the load adjusting portion () of the at least one connecting line () on the base substrate () is at least partially overlapped with an orthographic projection of at least one clock signal line on the base substrate ().

Display panel and display apparatus

Growing community of inventors

Beijing, China

Xuehuan Feng