Shanghai Ic R&d Center Co., Ltd

Chengdu Image Design Technology Co., Ltd.

Xuehong He

Xi Zeng

Hailing Yang

Yuan Yuan Zhang

Ying Luo

Huijie Yan

Changming Pi

Xiameng Lian

Pu Zhou

The present invention is to provide an image signal detection circuit, a control method, and a motion detection method. The image signal detection circuit comprises at least one acquisition module, the acquisition module comprises at least one acquisition sub-module, the acquisition sub-module comprises a capacitor to acquire the difference between a pair of two consecutive frames of pixel signals by taking a reference voltage as a reference. The image signal detection circuit and a motion detection circuit are structurally simple and easy to implement. It can realize motion detection at increased difference detection speed without analog-to-digital conversion.

Image signal detection circuit, control method and motion detection method

A method of removing fixed pattern noise, comprising: S: performing a single-frame segmented exposure on a pixel array; S: reading a of the pixel array, comprising: S: performing a soft reset, so as to set the reset signal of the pixel unit to an intermediate voltage, and reading a differential reset signal; S: performing a hard reset so as to set the reset signal of the pixel unit to a high voltage; S: turning on a transmission MOS transistor to enable an exposure signal of to photodiode to transmitted to the floating diffusion area, and reading a differential pixel transmission signal; S: subtracting the differential reset signal from the differential pixel transmission signal to obtain an exposure signal with fixed pattern noise removed. Another method is removing fixed pattern noise and an image sensor are further provided.

Method of removing fixed pattern noise

A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate. Compared with the existing polyline mode, the present disclosure has better linearity; and it can be easily extended to cascade multistage integrators.

System and method for regulating transfer characteristics of integral analog-to-digital converter

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Shanghai, China

Xuehong He