Avago Technologies General IP (singapore) Pte. Ltd.

Lsi Corporation

Avago Technologies International Sales Pte. Limited

Xuebin Wu

Shaohua Yang

Yang Han

Fan Zhang

Weijun Tan

Wu Chang

Haitao Xia

Yuqing Yang

Yoon Liong Liow

Shu Li

Bruce Alexander Wilson

Yu Kou

Dan Liu

Qi Zuo

Keke Liu

Rui Cao

Wei Zhang

Ming Jin

Avi Steiner

Lu Lu

Kelly K Fitzpatrick

Zhi Bin Li

Kaitlyn T Nguyen

Kapil Gaba

Jefferson Singlelon

An apparatus for decoding data includes a data decoding circuit configured to decode data encoded with an irregular low density parity check code based on a parity check matrix with non-uniform column weights, and at least one scaling circuit configured to scale values in the data decoding circuit with a scaling value that is dependent at least in part on a column weight of the likelihood values being scaled.

Irregular low density parity check processing system with non-uniform scaling

An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

Systems and methods for data processing with folded parity sector

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multiple codeword processing in a data processing system. An illustrative data processing system includes a processing circuit that processes unprocessed codewords, and provides failed codewords when the processing fails to converge. The system may further include an input buffer circuit that selectively stores a combination of at least one of the unprocessed codewords and at least one of the failed codewords. The input buffer circuit includes a first portion that maintains any of the unprocessed codewords and the failed codewords, and a second portion that maintains only the failed codewords.

Systems and methods for retaining non-converged data sets for additional processing

Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.

Systems and methods for correlation based data alignment

An apparatus for processing data includes a data detector configured to detect data values in data sectors to yield detected data, a data decoder configured to decode the detected data, wherein the data detector and the data decoder are configured to process the data sectors in a series of global iterations, a memory configured to store parity sector soft information, and a scheduler configured to control overlapping reprocessing of a failed sector in the data detector and the data decoder based on the parity sector soft information with processing of another data sector in the data detector and the data decoder.

Systems and methods for overlapping parity sectors

An apparatus for processing data includes a storage medium operable to store encoded data, and a read channel circuit with a low density parity check encoder operable to encode data to generate the encoded data, and a low density parity check decoder operable to decode the encoded data retrieved from the storage medium. The read channel circuit is operable to perform a column rotation on the encoded data prior to storage and after retrieval before decoding.

Non-binary low density parity check code column rotation

An apparatus includes a storage medium operable to store a number of data tracks, a read channel circuit operable to process the data tracks read from the storage medium, and a track quality classifier circuit operable to determine a track quality metric for the data tracks read from the storage medium. The track quality metric indicates whether a corresponding one of the data tracks that has failed to successfully process in the read channel circuit can be reprocessed within a track gap period.

Track quality classifier

Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.

Diversity loop detector with component detector switching

Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set. In one particular case, a system is disclosed that includes a stitching circuit and a data recovery circuit. The stitching circuit is operable to: receive a data set including at least a first fragment and a second fragment; replicate data from at least one of the first fragment and the second fragment as stitching values; and aggregate the first fragment with the second fragment with the stitching values between the first fragment and the second fragment to yield a combined data set. The data recovery circuit is operable to process the combined data set to yield an original data set.

Systems and methods for recovered data stitching

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data detection. As one example, a data processing system is described that includes a variance calculation circuit operable to calculate a variance of a data input; and a branch metric calculation circuit operable to calculate a branch metric based at least in part on the variance.

Systems and methods for floating variance branch metric calculation

Systems and method relating generally to data processing, and more particularly to systems and methods for fragmenting a data set and recovering the fragmented data set. As one example, a data processing system is discussed that includes: a fragmenting circuit operable to separate a data set into at least a first fragment and a second fragment; and a transfer packet formation circuit operable to: append identification information to the front of the first fragment, and at least a first M+N bits of the second fragment to the end of the first fragment to yield a first transfer fragment, and aggregate the first transfer fragment with other transfer fragments to yield an aggregate output.

Systems and methods for fragmented data recovery

A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

Read channel sampling utilizing two quantization modules for increased sample bit width

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing. As an example, a data processing system is discussed that includes a sample averaging circuit operable to average digital samples from an analog to digital converter circuit over multiple instances of an analog input to yield an X-average output, and a selector circuit operable to select one of the digital samples or the X-average output as a processing output.

Systems and methods for data retry using averaging process

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for coasting one or more calibration loops based upon identification of a probability of data inaccuracies. One embodiment is a data processing system that includes: a defect detector circuit operable to identify a defect region during a first pass processing of a received data set; a defect location buffer operable to maintain an indication of the defect region in the received data set; and a calibration circuit operable to adaptively update a calibration output during a second pass processing of the received data set, where updating the calibration output is disabled for one or more samples of the received data set corresponding to the indication of the defect region.

Systems and methods for calibration coasting in a data processing system

A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.

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San Jose, CA, United States of America

Xuebin Wu