United Test and Assembly Center Limited

Utac Headquarters Pte. Ltd.

Xue Ren Zhang

Chin Hock Toh

Ravi Kanth Kolan

Yi Sheng Anthony Sun

Yi-Sheng Anthony Sun

Librado Amurao Gatbonton

Keng Yuen Au

Reynaldo Vincent Hernandez Sta Agueda

Bee Liang Catherine Ng

A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Packaging structural member

A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.

Semiconductor package and method of packaging semiconductor devices

Growing community of inventors

Singapore, Singapore

Xue Ren Zhang