Sandisk Technologies Inc.

Xue Qing Cai

Jiahui Yuan

Deepanshu Dutta

Henry Chin

A method for multi-stage programming of a non-volatile memory structure includes the step of initiating a programming operation with respect to a memory block. The method also includes the step of applying a programming algorithm to the memory block. The programming algorithm comprises at least a first programming stage and a second programming stage. Between the first programming stage and the second programming stage, the method additionally includes applying a time delay according to a pre-determined amount of time. Further, the pre-determined amount of time may be defined as the amount of time that, according to a probabilistic function, permits de-trapping of any charges unintentionally trapped within a memory cell of the memory block as a result of the first programming stage.

Reliability improvement through delay between multi-stage programming steps in non-volatile memory structures

Techniques are described for programming memory cells without performing a verify test, where the programming is followed by a short circuit test. In one aspect, an initial programming is performed on memory cells of a first word line of a block using a program pulse with an initial magnitude, Vpgm. By reading the memory cells, Vpgm can be optimized for programming subsequent word lines. The subsequent word lines may be programmed using a no-verify program operation followed by a word line short circuit test, for one or more word lines involved in the program operation. The short circuit test can be performed concurrently on a single word line, multiple word lines and/or one or more sub-blocks of a block, based on an amount of write data which can be storage by a controller.

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Fremont, CA, United States of America

Xue Qing Cai